MSPM0G3507: ADC does not propperly start and stop

Hi Norbert,

I need some time to check the details carefully, it does have a lot things inside the document.

Thanks for your patience.

B.R.

Sal

Hi Norbert,

For the first case, where users clear ENC bit, it can been seen that the ADC execute the conversion for some reason.

I have a guess below:

After ENC is clear, the ADC is active to next trigger signal. If all the channels are configured require valid trigger, then it will convert one following channel. If only the last channel configured as valid trigger, then it will end at the last channel.

To quick verify it, I suggest you read the RIS bit to see if MEM3 is loaded if you clear ENC after MEM0 and before MEM1. -> Make sure in DMA done interrupt, you will clear RIS bit of MEM0~MEM3 (channel 0~3).

-> If the suspect is correct, only the MEM2 will be set with next timer trigger. The MEM3 will never be set.

B.R.

Sal

As for the workaround, I have some proposal below:

#1 Add DMA disable in ADC module

Add below:

DL_ADC12_disableDMATrigger(ADC1, DL_ADC12_DMA_MEM0_RESULT_LOADED << (num_of_samples-1));  // trigger on last sample

DL_ADC12_disableDMA(ADC1);

to disable DMA transfer in ADC module also.

Note:

I see you mentioned related thing in the doc, but I do not see the disable behavior in the ADC_stop().

#2 Stop Timer Event Generation to disable ADC conversion

stop timer -> DL_TimerG_disableEvent -> enable timer.

Directly disable event might work without stopping timer.

#3 Reset ADC and Re-configure ADC

To stop ADC:

clear ENC bit, reset ADC

To start ADC:

enable ADC power, configure ADC with preset parameters, set ENC bit to receive Timer trigger event

B.R.

Sal

Hello Sal, thank you for your answers!

I'm a colleague of Norbert's.

Sal Ye said:

After ENC is clear, the ADC is active to next trigger signal. If all the channels are configured require valid trigger, then it will convert one following channel. If only the last channel configured as valid trigger, then it will end at the last channel.

Yes, that is something we've seen as well and shown in the screenshots. The problem was rather in the unclear documentation of this behavior in the reference manual that led to much time spent on investigating the root cause of the side effects it causes. Should we expect the update of the manual with clarified explanations? The second point of "Main questions" is still open as well.

Sal Ye said:

As for the workaround, I have some proposal below

Can you please clarify if these workarounds are related to the first or the second problem?

Sal Ye said:

#1 Add DMA disable in ADC module

In our example, we are disabling the DMA channel in ADC_Stop() and (in the second, "fixed", example), clearing the pending DL_ADC12_DMA_MEM3_RESULT_LOADED before enabling the channel in ADC_Start(). What creates the necessity to disable the DMA trigger as well, and what problems should it fix? We would like to have a deeper understanding of the system to address potential future problems more effectively.

Sal Ye said:

#2 Stop Timer Event Generation to disable ADC conversion

As I understand, it is a potential "replacement" for ADC_Stop(), right? To stop the triggering, instead of forcing ADC to stop conversions? While this is a robust approach, we still would like to concentrate on the ways to stop ADC itself, without interacting with the peripherals that trigger it.

Sal Ye said:

#3 Reset ADC and Re-configure ADC

This is the approach we want to avoid in our system. ADC configuration must remain untouched while we are restarting it.

The answers to the questions from the document ("Main questions", "Side questions and clarification") are in progress, and we should expect them sometime later, right?

Please let us know if something is unclear or unreproducible from the prepared document or code example.

BR,
Oleksandr

Hi Oleksandr,

Oleksandr Ohlashennyi said:

Should we expect the update of the manual with clarified explanations? The second point of "Main questions" is still open as well.

Sure, I will discuss internally to see how to add additional clarifications on this part. Maybe an application note is preferred as this is a unique application scenario. Please let me know if there any new findings from you side on this case.

Oleksandr Ohlashennyi said:

Can you please clarify if these workarounds are related to the first or the second problem?

The workarounds is proposed to fix this specical issues: disable ADC conversion just before the last channel which trigger the DMA done interrupt, might result in a interrupt timing conflict on software logic.

Oleksandr Ohlashennyi said:

What creates the necessity to disable the DMA trigger as well, and what problems should it fix? We would like to have a deeper understanding of the system to address potential future problems more effectively.

The root cause is not clear for now. I will do some experiment test to dig more details and I am appericated if you can share some findings towards the proposal.

Oleksandr Ohlashennyi said:

The answers to the questions from the document ("Main questions", "Side questions and clarification") are in progress, and we should expect them sometime later, right?

Yes, while I now prioritize the ADC ENC behavior and DMA trigger logic research.

The issues about the second question -> interrupt lost, I can check later whent the first problem is clear clarified. -> I think if the first problem saved, we might not encounter the second problem and we can dig it later.

B.R.

Sal

Sal Ye said:

The root cause is not clear for now. I will do some experiment test to dig more details and I am appericated if you can share some findings towards the proposal.

Understood, thank you for the clarification. I've tested this proposal and see the same behavior as in the "second" implementation of ADC_Stop -> ADC is stopped, I don't observe the redundant interrupts after the stop function is called. However, the second issue is still there: at a random point in time, ADC is not started again after the start function and stuck in the state described in "Second problem faced (conditions to reproduce are unclear)" of the attached document

We will wait for further clarifications from your side and let you know in case of additional findings.

BR,
Oleksandr

Hi Oleksandr,

Thanks for the feedback, I'll take a look into these two issues.

B.R.

Sal