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TMS570LS1224: FLASH FEDACSTATUS register contains unknown data at power-up

PauloP
Prodigy 240 points

Part Number: TMS570LS1224

The register description for several FLASH registers includes the sentence:

This register is not changed with the reset signal and contains unknown data at power-up.

Note: This appears to override the -u allocation for value after reset (unchanged value on internal reset, cleared on power up)

The above sentence is not included in the register description for the Flash Error Detection and Correction Status Register (FEDACSTATUS).

During development I have noted that the value assigned to FEDACSTATUS bit 8 (B1_UNC_ERR ) is not cleared on a power on reset.

Questions:

a) Is the behaviour I have described for FEDACSTATUS bit 8 as expected?

b) Does the sentence "This register is not changed with the reset signal and contains unknown data at power-up." also apply to FEDACSTATUS and if not which bits are not cleared on a power on reset?

  • 0
    TI__Guru* 77906 points

    Hi Paulo,

    PauloP said:
    a) Is the behaviour I have described for FEDACSTATUS bit 8 as expected?

    The Flash Error Detection and Correction Status Register (FEDACSTATUS) contain latched error status bits generated by the Flash ECC logic.

    Some of these bits:

    Latch when an ECC error occurs, remain set until explicitly cleared by software

    PauloP said:
    b) Does the sentence "This register is not changed with the reset signal and contains unknown data at power-up." also apply to FEDACSTATUS and if not which bits are not cleared on a power on reset?

    is not explicitly written for FEDACSTATUS, but similar behavior effectively applies to parts of it, particularly the error status bits.

    However, the more precise rule is:

    ECC error status bits (like B1_UNC_ERR) will be latched when an ECC error occurs, remain set until explicitly cleared by software.

    --
    Thanks & regards,
    Jagadish.