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MSPM0G1105: MSPM0G ADC sampling time limitations when used with PGA

Andrew Witte
Prodigy 10 points

Part Number: MSPM0G1505

I'm trying to understand more about the "Tsample_PGA" specification for the MSPM0G ADC when used with the internal op-amp. These sampling times are much longer than those for the ADC alone. 

  • Am I correct to believe that this specification is basically due to a settling time limitation based on the output impedance of the PGA?
  • As a result, I would expect selecting a sample time below Tsample_PGA to cause worsened noise and linearity performance of the ADC (below published specs). Are there any further consequences I should be aware of?
  • 0
    TI__Genius 12805 points

    Hi Andrew,

    Andrew Witte said:
    Am I correct to believe that this specification is basically due to a settling time limitation based on the output impedance of the PGA?

    Yes, when PGA output is internally connected to ADC input, we need to consider the ADC input impedance impacted by PGA when setting sampling time.

    Andrew Witte said:
    As a result, I would expect selecting a sample time below Tsample_PGA to cause worsened noise and linearity performance of the ADC (below published specs). Are there any further consequences I should be aware of?

    Just make sure your ADC sampling time is set larger than Tsample_PGA spec if PGA is used as ADC input.