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AM263P4-Q1: RBL / SBL Checklist?

Kier
Mastermind 9655 points

Part Number: AM263P4-Q1

Hello,

In DevBoot mode, I am able to run custom* SBL on our custom* HW using a modified sbl_load.js:

image.png

After a CPU reset, the .mcelf application runs.

My problem is that when I put the SOC boot pins to QSPI 4S mode, the custom SBL and therefore application do not run.

After power-on, If I connect the debugger (without loading a program or resetting), the PC does not correlate with a symbols in my SBL code:

image.png

I conclude the RBL did not load my SBL. However, I'm not sure what to check now.

I have a asked the HW team to configure the boot mode in 1S but in case this does not resolve the issue, what is my next move please?

  • Is there a checklist of items or flowchart to eliminate silly errors?
  • Are there any registers I can check which provide clues to the cause of RBL failure?

 

*The custom SBL uses 'sbl_ospi_multicore_elf' in mcu_plus_sdk_am263px_11_00_00_19 as a baseline with modifications for the S25FL128SAGMFI000 - Quad SPI flash | Infineon Technologies flash and removal of I2C and EEPROM which aren't relevant for our HW.

The only other difference is that we have special hsmRtImg.h provided by TI (Nikhil Dasan) in order to open the TRACE port.

  • 0
    TI__Guru 59360 points
    Kier said:
    My problem is that when I put the SOC boot pins to QSPI 4S mode, the custom SBL and therefore application do not run.

    Please make sure that the QE(Quad enable bit) is set before you are trying to boot from flash in 4s boot mode. This is something I have seen as a common issue in board bring up.

  • 0 in reply to Nilabh Anand
    TI__Guru 59360 points

    Sequence to enable quad mode (1s-1s-4s) changes from flash to flash. According to the JEDEC standards, there are 7 different types of Quad Enable(QE):

    • 0 : Device does not have a QE bit. Detects based on instruction.

    • 1 : QE is bit 1 of status register 2. It is set via Write Status with two data bytes where bit 1 of the second byte is one. It is cleared via Write Status with two data bytes where bit 1 of the second byte is zero. Writing only one byte to the status register has the side-effect of clearing status register 2, including the QE bit.

    • 2 : QE is bit 6 of status register 1. It is set via Write Status with one data byte where bit 6 is one. It is cleared via Write Status with one data byte where bit 6 is zero

    • 3 : QE is bit 7 of status register 2. It is set via Write status register 2 instruction 3Eh with one data byte where bit 7 is one. It is cleared via Write status register 2 instruction "0x3E" with one data byte where bit 7 is zero. The status register 2 is read using instruction "0x3F".

    • 4 : QE is bit 1 of status register 2. It is set via Write Status with two data bytes where bit 1 of the second byte is one. It is cleared via Write Status with two data bytes where bit 1 of the second byte is zero. Writing one byte to the status register does not modify status register 2.

    • 5 : QE is bit 1 of the status register 2. Status register 1 is read using Read Status instruction "0x05". Status register 2 is read using instruction "0x35". QE is set via Write Status instruction 01h with two data bytes where bit 1 of the second byte is one. It is cleared via Write Status with two data bytes where bit 1 of the second byte is zero.

    • 6 : QE is bit 1 of the status register 2. Status register 1 is read using Read Status instruction "0x05". Status register 2 is read using instruction "0x35", and status register 3 is read using instruction "0x15". QE is set via Write Status Register instruction "0x31" with one data byte where bit 1 is one. It is cleared via Write Status Register instruction "0x31" with one data byte where bit 1 is zero.

    This config is present as part of syscfg flash->Protocl enable configuration->Quad Enable type

  • 0 in reply to Nilabh Anand
    Mastermind 9655 points

    Many thanks Nilabh. It does look like QE is not enabled by default.

    I shall have to figure out how to program the NV register in the Infineon flash. New territory for me.

  • +1 in reply to Kier
    TI__Guru 59360 points

    A simple way to program is to run the OSPI flash io example to do read/write in 4s mode, in the program, configure the QE bit.

    The program will configure the QE bit, since QE bit is Non volatile, it wil take effect from next boot cycle onwards

  • 0 in reply to Nilabh Anand
    Mastermind 9655 points

    That's a great tip, many thanks indeed.

  • 0 in reply to Kier
    TI__Guru 59360 points

    Let me know if you have any further questions.

  • 0 in reply to Nilabh Anand
    Mastermind 9655 points

    Again, thanks Nilabh. I just fixed it with your advice.

    For other readers: I modified my SBL to use 1S-1S-4S, it was 1S-1S-1S initially because I was being (too) cautious:

    Then I ran it with the load_sbl Java script in the debugger. As per Nilabh's advice, this appears to have enabled quad mode permanently and the now it boots in OSPI 4S mode to my application.