F29H85X-SOM-EVM: the issue about power on and crystal oscillators

Hi Jenny 

Let me find the right person to address the issue. Please expect response in 1-2 days.

Thank you 

Amir Hussain

Hi Amir,

The customer has an urgent case, so pls give higher priority to these questions. 

Hi Jenney,

Jenney Ni said:

Regarding the power-on slope, our test focuses on the fastest section of the power-up slope. I’d like to ask if the datasheet specification for the rising slope is also based on the fastest segment?

This is correct, you will see a linear region in the power-up waveform. The datasheet specs are based on this linear region 

Jenney Ni said:

During power-down, when XRSN drops, VDD3V3 drops to 2.73V but then recovers. Will the repeated assertion/de-assertion of XRSN caused by such power supply jitter during power down cause any problems?

Can you reupload the image? It seems it's not displaying in your message

Jenney Ni said:

What is the required ripple for each power rail? I couldn’t find this specification in the datasheet.

Voltage ripple is typically not a concern as long as the voltage remains within the recommended operating voltage. See below diagram for reference values. Proper decoupling of voltage rails should be sufficient, please refer to datasheet recommendations accordingly for each voltage rail

Jenney Ni said:

For external active crystal oscillators, I didn't find any requirements for the peak-to-peak amplitude in the datasheet.

We primarily use passive, such as 830108207209 which does not specify voltage and leverages internal MCU clocking circuitry for deriving the clock. For active oscillators, as long as it does not exceed 3.3V, it is fine

Jenney Ni said:

Is it necessary to add a capacitor to XTAL1? Your datasheet mentions it as a recommendation, but there is no such capacitor in the development board

Some clocking configuration requires external capacitor, others do not, please see below for examples

Regards,

Peter

Hi Peter,

add the picture:

During power-down, when XRSN drops, VDD3V3 drops to 2.73V but then recovers. Will the repeated assertion/de-assertion of XRSN caused by such power supply jitter during power down cause any problems?

Regards,

Jenney

Hi Peter,

You mean 'power-on and power-off of the device abnormally will cause the long-term damage',right? The internal power management module needs the software development, right? Where i can get the docments about this?

Regards,

Jenney