MSPM0L1305: Migrating from LPC804 (MLIB fixed‑point) to MSPM0L1305 — Will CMSIS‑DSP give similar cycle performance?

We are migrating from an NXP LPC804 design that uses MLIB fixed‑point functions (frac16/frac32, MAC/MSU with rounding, saturating math). On LPC804 these routines run with very small cycle counts because they are optimized for Cortex‑M0+.

On MSPM0L1305, fixed‑point math is supported through CMSIS‑DSP (q15/q31 types and DSP functions). Since both LPC804 and MSPM0L1305 use the same ARM Cortex‑M0+ core with identical instruction timing (ADD/SUB/SHIFT/MUL are 1‑cycle operations per the Cortex‑M0+ TRM), I want to confirm:

Can CMSIS‑DSP on MSPM0L1305 achieve cycle performance comparable to MLIB on LPC804?

Are there any MSPM0‑specific considerations (flash wait states, pipeline, memory access) that may affect cycle counts?

Looking for guidance on expected performance parity between MLIB and CMSIS‑DSP on MSPM0L130x.

Thanks!