AM2432: GPMC access sequence of read and write

Hi Zekun,

Please help me understand your question better. 

Do you mean is it okay to have this sequence on GPMC:

CS assert -> read data from FPGA -> write data to FPGA -> CS de-assert ?

I can see 4 waveforms on the screen. Which color is which?

What is the mode of GPMC operation? 

Thanks,

Stan

Hi Stanislav Stilyanov:

We are using a single-read/write mode, employing a shared approach between DMA and direct read/write. DMA is used for reading and writing large amounts of data, while direct read/write is used for small amounts of data.
Then we captured this waveform, which cannot be used, causing data errors
In addition, after we disable the DMA function and use direct read-write mode, this waveform will no longer exist

Thanks,

Jimmy

Hi Jimmy

Thanks for the reply. Want to check one thing with you. 

There will be direct R/W and DMA R/W co-existing in your scenario, right? So how do you know when to trigger the DMA read when you are doing a direct R/W?

If you are doing a direct R or W, let say an interrupt is coming and trigger the DMA R or W, does this scenario happen in your real case?

Stanislav Stilyanov  Please share your ideas if this is the expected behavior, Thanks.

Thanks

Zekun

Hi Zekun

DMA reading and direct reading will definitely coexist due to multi-threaded operations, but I am not sure when DMA will operate GPMC.

Indeed, DMA read/write operations may be inserted into the direct read/write process, or direct read/write operations may be inserted into the DMA read/write process.

Thanks,

Jimmy

Hi  Jimmy

So there is no priority difference assigned on multi-thread, like direct R/W in low priority, DMA R/W in high priority, right?

Can you elaborate this waveform causing the data error?

Like the direct R/W data is error while the DMA R/W data is correct, or on the other hand DMA is error while direct R/W is correct?

But the way, what is the frequency of this issue in your circumstance?

Thanks

Zekun

Hi Zekun

Yes, there is no difference in priority between direct read/write and DMA read/write. We have two threads with different priorities that operate on GPMC. Both direct read/write and DMA read/write exist in each thread. The criterion for distinguishing between direct read/write and DMA read/write is the amount of data (DMA read/write is used for data larger than 128 bytes)

This waveform indicates the presence of both read and write operations within a single chip select signal, leading to confusion for our FPGA regarding whether the controller intends to perform a read or write operation.

In the case of a large amount of data, this waveform appears once every ten or so seconds.

Thanks,

Jimmy

Hi  Jimmy

So in one high priority thread:

Logis is

if (Large amont)

DMA R/W, else

Direct R/W

end

Another low priority thread:

if (Large amont)

DMA R/W, else

Direct R/W

end

Is this right?

Thanks

Zekun

Hi Zekun

Yes, that's the logic

Thanks,

Jimmy

Hi Jmmy

So the logic and the waveform match. I do not think it is abnormal issue. 

What is the your expectation to this observation? 

Thanks

Zekun

Hi Zekun

I believe that whether it's the CPU operating GPMC or the DMA operating GPMC, even if commands are issued simultaneously, the GPMC controller should not introduce any timing confusion, which could prevent external devices from recognizing the timing sequence.

Thanks,

Jimmy

Hi Stan

Any comments here about Jimmy's query would be appreciated.Stanislav Stilyanov 

Thanks

Zekun

Hi Zekun,

It looks to me more like software query than hardware one. I will need to reach out to software expert.

thanks,

Stan