Part Number: TMS320F28388D
Hi everyone,
I’m working on implementing a multi-byte I2C register read without using FIFO. I’ve written the following function to read multiple bytes from a slave device:
#define CMI2C_DELAY_IN_US = 50;
//
// cmi2c single register read
//
uint8_t cmi2c_ReadReg(uint8_t slave, uint8_t reg, uint8_t data[], uint8_t len)
{
uint8_t d = 1, err;
// Wait until bus free
err = cmi2c_isMasterBusy();
if (I2C_OK != err)
{
return err;
}
// Send Slave address
I2C_setSlaveAddress(I2C0_BASE, slave, I2C_MASTER_WRITE);
I2C_putMasterData(I2C0_BASE, reg);
I2C_setMasterConfig(I2C0_BASE, I2C_MASTER_CMD_BURST_SEND_START);
// Wait until bus free
err = cmi2c_isMasterBusy();
if (I2C_OK != err)
{
return err;
}
DEVICE_DELAY_US(CMI2C_DELAY_IN_US);
// Read First Byte
I2C_setSlaveAddress(I2C0_BASE, slave, I2C_MASTER_READ);
I2C_setMasterConfig(I2C0_BASE, I2C_MASTER_CMD_BURST_RECEIVE_START);
// Wait until bus free
err = cmi2c_isMasterBusy();
if (I2C_OK != err)
{
return err;
}
data[0] = I2C_getMasterData(I2C0_BASE);
DEVICE_DELAY_US(CMI2C_DELAY_IN_US);
for (; d < len - 1; d++)
{
I2C_setMasterConfig(I2C0_BASE, I2C_MASTER_CMD_BURST_RECEIVE_CONT);
// Wait until bus free
err = cmi2c_isMasterBusy();
if (I2C_OK != err)
{
return err;
}
data[d] = I2C_getMasterData(I2C0_BASE);
DEVICE_DELAY_US(CMI2C_DELAY_IN_US);
}
DEVICE_DELAY_US(CMI2C_DELAY_IN_US);
// Read Last Byte
I2C_setMasterConfig(I2C0_BASE, I2C_MASTER_CMD_BURST_RECEIVE_FINISH);
// Wait until bus free
err = cmi2c_isMasterBusy();
if (I2C_OK != err)
{
return err;
}
data[len - 1] = I2C_getMasterData(I2C0_BASE);
return I2C_OK;
}
Issue:
-
On the logic analyzer, the I2C transaction looks correct (start, address, repeated start, and data bytes are all proper).
-
However, the data stored in the buffer (
data[]) is not properly organized or sometimes incorrect. -
Interestingly, the code works perfectly in debug mode, but fails or gives inconsistent results in normal run mode.
what is the problem in this code kindly guide me.
