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AM13E23019: ECC check exceptions

Oleksandr Ohlashennyi
Prodigy 131 points

Part Number: AM13E23019

  1. In TRM its mentioned “11.1.6.2 ECC Error Handling The read interface detects and corrects single bit errors in a 64-bit flash word (SEC) and detects dual-bit errors in a 64-bit flash word (DED). ECC checks are ignored for an “all-1’s” or “all-0’s” scenario.” The question is what all-1s and all 0s scenario mean? Background: we use ECC checks to check safety of flash, and in case some of the content (like all 0s and all1s) is not checked - it can violate safety requirements.

  2. Does DMA access to flash have ECC protection? TRM has confusing information:
    image.pngimage.png 


BR,
Oleksandr

  • +1
    TI__Mastermind 32693 points

    Hello Oleksandr,

    Apologies for the delayed response while this was being properly assigned.

    1) This means that the data block the ECC is running on consists of all 0 values or all 1 values. The ECC cannot be calcuated if all the bits are the same value. There is some information regarding these details from a previous device. Please review the information here: https://www.ti.com/lit/an/spna139/spna139.pdf

    2) The DMA can determine address/data errors and are logged in the ADDERR and DATAERR bits. I will file a ticket to have the misleading note text updated.

    Best Regards,

    Zackary Fleenor

  • 0 in reply to Fleenor
    Prodigy 131 points

    Hello Zackary, thank you for your answer!

    This helped a lot. But since this is a safety-related topic for us, I want to clarify some details:

    1. This is indeed a useful document, but I want to understand how applicable the information is for the AM13E2x:

          1.a) ECC is always ignored when data bits contain only 1’s or 0’s, with no exceptions or control over this feature?

          1.b) This applies to the whole Flash on am13e2x? Not only for some of the flash banks, like FEE that document mentions?

          1.c) "Probability of any one bit failing" I assume we do not have this information for our device, as it highly depends on the environment and flash condition itself?

    2. This means, when accessing corrupted Flash with DMA, we will face a data error in the DMA, and not the NMI?

    BR,
    Oleksandr

  • 0 in reply to Oleksandr Ohlashennyi
    TI__Mastermind 32693 points

    Hello Oleksandr,

    Completely understand your need for clarification, especially given the safety-related nature of this topic – we're happy to provide as much detail as possible.

    1. You are correct to ask about the applicability to the AM13E230x. While ECC controller implementations differ between devices, the fundamental principles remain the same.

      1a) Yes, the AM13E230x Flash ECC does not perform checks on data blocks containing all 0s or all 1s. This is a hardware limitation and there is no control to override this behavior.

      1b) Yes, for the AM13E230x, ECC protection is applied to the entire MAIN Flash Bank (all partitions). It does not only apply to the FEE regions as described in the document as this is a specific implementation for the previous device.

      1c) Yes, there is a high dependence on environmental and flash conditions. We do not have a readily available, guaranteed "probability of bit failure" numbers. I will inquire internally if any reliability testing data is available, but it’s important to understand that any number provided would be based on controlled conditions and may not reflect your specific operating environment. We can share any information we find, with the caveat that it's an estimated value.

    2. In the case of accessing corrupted flash via DMA, both the DMA DATAERR flag and the NMI FLASH DED/SEC flags would be asserted. The DMA error is detected during the transfer, while the NMI signal indicates a more fundamental ECC failure detected by the flash controller itself. Both mechanisms are triggered to signal a data integrity issue.

    Best Regards,

    Zackary Fleenor