AM13E23019: PGA MUX

Hello Zackary,

Sorry, I wrongly clicked "This resolved my issue". It is not still closed.

Regarding 1) and 2), it is not still clear what is the true for PGA_NEG_SHARED function.
What is the right way to use PGA_NEG_SAHRED function? (Shared negative inputs between AMPs but only using one external pin.)

Regards,
Oba

Hello Zack,

Thanks for your detail answer.  

There is one confusion in the summary.

Whle item 4 says PGA0_INM2 and PGA2_INM2 can't be used for other function,
it also says that " One remaining open item worth confirming with TI: whether PGA0_INM2 and PGA2_INM2 can be reconfigured as GPIO via the pin mux when PGA_NEG_SHARED is active, and the exact electrical loading implications of driving one pin into three amplifier negative terminals simultaneously. "
Is it remaining open item?

And is it OK to answer "M4 and M5 can be used and we will update the TRM" to the customer?

Regards,
Oba

Hey Oba,

I have corrected the original reply.

Yes, this is okay to tell the customer.

Best Regards,

Zackary Fleenor

Hello Zackary,

Thanks for your support.

Regards,
Oba

Hello Zackary,

I'm testing the PGA_NEG_SHARED function with the EVM.
But it doesn't work at all. Then I have some questions.

1) 
At first, I would like to understand true assignment for MMUX.

Figure 18-1 says that 
MMUX=2 -> INM3
MMUX=3 -> INM2
MMUX=4 -> INM1
MMUX=5 -> INM0

Table 18-1 looks like saying that 

MMUX=2 -> INM0
MMUX=3 -> INM1
MMUX=4 -> INM2
MMUX=5 -> INM3

Table 18-14 says that

MMUX=2 -> INM1
MMUX=3 -> INM2
MMUX=4 -> reserved
MMUX=5 -> reseved

What is true?

2)

Assumed Table 18-1 is true.

The below block diagram comes from TRM for this function.

PGA_NEG_SHARED bus (green line) is connected to MMUX=2 of PGA2 which means PGA2_INM0.
So from this block diagram, PGA2_INM0 is shared with all PGA0/1/2. Is this understanding correct?

If it is correct, each MMUX=3 of PGAx is connected like the below.

PGA0 -> A1_IN11 / A2_IN24 / PGA0_INM1 / PGA1_INM2
PGA1 -> A1_IN13 / A2_IN19 / CMP2_DACL1 / CMP1_HN1 / PGA1_INM1
PGA2 -> A1_IN12 / CMP3_HN0_LN0 / PGA2_INM1

And  "A0_IN4 / A2_IN21 / CMP1_HP0_LP0 / PGA0_INM0 / PGA0_INP2 / PGA2_INM0" is connected to PGA_NEG_SHARED bus.
It means 4 pins have to be used for this function.

It looks strange. I feel something is wrong. Actually, it doesn't work at all.
Could you tell me what is true?

When MMUX=3 and NMUX=1 in all PGAx, what pin is negative input signal for shared?

3)
Could you tell me the difference between MMUX=0(VSSA) and MMUX=1(VSSA_NINV)?

Regards,
Oba

Hello Oba,

Please allow me a few days to formulate the proper response here. We will implement some updates in the PGA chapter in the upcoming release to provide better clarification here.

Best Regards,

Zackary Fleenor

Sure. Thanks for your support.

Regards,
Oba

Hello Oba,

Thank you for your patience while we investigated these discrepancies. I want to address each of your questions carefully, as there are indeed documentation inconsistencies across Table 18-1, Table 18-14, and Figure 18-1 that have caused significant confusion. We are actively working to correct these in the next TRM release.

1. MMUX Assignment — What Is True?

After internal verification, the correct MMUX mapping is as follows:

Table 18-1 is the most accurate reference. Figure 18-1 and Table 18-14 contain labeling errors that will be corrected. We apologize for the confusion this has caused.

2. How PGA_NEG_SHARED Actually Works — Corrected Explanation

Based on the correct MMUX mapping above, here is the accurate description of the PGA_NEG_SHARED function:

The PGA_NEG_SHARED bus is an internal signal bus that connects one designated external physical pin to the negative input terminals of all three PGAs simultaneously. The shared physical pin is PGA2_INM0.

When configuring PGA_NEG_SHARED:

• Set MMUXSEL = 2 on PGA0 and PGA1 — this routes their negative inputs to the PGA_NEG_SHARED bus
• PGA2 naturally connects through its own INM0 pin, which is the physical source of the shared bus
• Set NMUXSEL = 1 on all three PGAs to enable the inverting path through the feedback network (Ria)

The single external pin you connect your shared negative reference to is PGA2_INM0.

Regarding your earlier guidance that MMUXSEL=3 and NMUXSEL=1 should be used — I want to correct that. Based on our internal review, MMUXSEL=2 (INM0) is the correct selection for PGA0 and PGA1 when using PGA_NEG_SHARED, not MMUXSEL=3. The previous response was based on incorrect documentation, and I sincerely apologize for the misleading information that likely contributed to your testing failures.

3. Difference Between MMUX=0 (VSSA) and MMUX=1 (VSSA_NINV)

• MMUX=0 (VSSA): Connects the negative input of the PGA directly to VSSA (analog ground). This is used when you want the PGA to amplify a single-ended signal referenced to ground, with no external pin required for the negative terminal.

• MMUX=1 (VSSA_NINV): Connects VSSA to the non-inverting side of the internal feedback resistor network rather than directly to the inverting input node. This configuration is used for specific gain topologies where the feedback network reference point needs to be grounded, but the inverting terminal itself remains available for an external signal. This is a more specialized use case and is distinct from a simple ground connection.

In most standard single-ended gain configurations, MMUX=0 is the appropriate choice.

Summary of Corrected PGA_NEG_SHARED Configuration

1. Connect your shared negative reference signal to PGA2_INM0 on your PCB
2. On PGA0 and PGA1, set MMUXSEL = 2, NMUXSEL = 1
3. On PGA2, set MMUXSEL = 2 (or the default INM0 path), NMUXSEL = 1
4. Set PMUXSEL on each PGA independently to match your positive input pin
5. PGA0_INM0 and PGA1_INM0 pins will not be available for other functions in this configuration

We will update the TRM to reflect the correct MMUX assignments and provide a clear PGA_NEG_SHARED configuration example in the next release. Again, I apologize for the incorrect guidance provided earlier in this thread.

Please let me know if this resolves the issue or if further clarification is needed.

Best Regards,

Zackary Fleenor

Hello Zackary,

Thanks for the information.
Today, I tested it with the Launchpad. But sill it didn't work at all.

I set MMUXSEL=2(INM0) and NMUXSEL=1 in all 3 PGAs.
I also set PMUXSEL=0(INP0), subtractor mode, PGA gain value of 2 or -1, in all PGAs

PGA0 and PGA2 worked well (I think it is because INM0 pin is physically shared), but PGA1 didn't work.
I could see the same voltage as PGA0_INP0 on both PGA1_OUT and PGA1_INM0.
Something looked wrong.

Have you checked the behavior on an actual device?

Regards,
Oba

Hello Oba,

Thank you for your continued patience and for providing your hardware test results — this is very helpful diagnostic information.

Your observation that PGA0 and PGA2 work correctly but PGA1 does not is a critical data point, and I want to be transparent with you about where we are.

Why PGA1 May Be Behaving Differently

Based on your test results and a deeper review of the pin descriptions in the AM263x datasheet, we believe we have identified the root cause of the PGA1 failure:

Per the datasheet pin table, PGA1_INM0 (M0) is located on a physically different pin than PGA0_INM0 and PGA2_INM0. Specifically:

• PGA0_INM0 and PGA2_INM0 share the same physical pin grouping that connects to the PGA_NEG_SHARED internal bus
• PGA1_INM0 is on a separate physical pin (shared with PGA0_P1), meaning MMUXSEL=2 on PGA1 does NOT route through the PGA_NEG_SHARED bus the same way it does for PGA0 and PGA2

This explains exactly the symptom you observed:

• PGA0 and PGA2 → working  (their INM0 pins connect to the shared bus)
• PGA1 → not working  (its INM0 pin is physically distinct and not on the shared bus path)

Recommended Configuration to Try for PGA1

Based on our review, PGA1 may require MMUXSEL=6 (M4) or MMUXSEL=7 (M5) — the globally shared M4/M5 paths — rather than MMUXSEL=2, in order to properly connect to the PGA_NEG_SHARED bus.

Please try the following configuration:

The M4 (MMUXSEL=6) and M5 (MMUXSEL=7) paths are the dedicated global shared input routes explicitly described in the TRM as "Equivalent to a global PGA_NEG_SHARED" — these may be precisely what is needed for PGA1 to participate in the shared negative input configuration.

Important Transparency Note

I want to be fully honest with you: we are still in the process of hardware-level verification of the complete PGA_NEG_SHARED configuration on an actual device. This thread has unfortunately involved multiple documentation inconsistencies that have made it difficult to provide confident guidance without physical validation.

To properly close this out, we are pursuing the following internally:

1. Hardware validation on a LaunchPad/EVM to confirm a working three-PGA shared configuration with register dumps and measured waveforms
2. Definitive clarification of PGA1's routing to the PGA_NEG_SHARED bus (MMUXSEL=2 vs. MMUXSEL=6/7)
3. TRM corrections to reconcile Figure 18-1, Table 18-1, and Table 18-14, and to add a clear PGA_NEG_SHARED configuration example

In the Meantime — Additional Diagnostic Questions

To help us narrow this down while hardware validation is underway, could you share:

1. What silicon revision/stepping is on your LaunchPad? (This is typically printed on the device or visible in the device ID register)
2. When PGA1 fails, is PGA1_OUT exactly equal to PGA1_INP0, or is there some offset? This would help confirm whether the gain path is active at all
3. Have you tried setting MMUXSEL=6 or MMUXSEL=7 for PGA1 specifically?

I sincerely apologize for the multiple rounds of correction in this thread. The documentation inconsistencies in the PGA chapter have made this a more difficult investigation than it should be, and your hardware testing has actually provided us with valuable diagnostic information that is helping to isolate the true behavior of this feature.

We will follow up as soon as hardware validation results are available.

Best Regards,

Zackary Fleenor

Hello,

I wanted to try the evaluation you suggested, but unfortunately, my Launchpad looks like be damaged. I'm ordering new one.
After receiving it, I'll try again.

Regards,
Oba

Hello,

I got the new Launchpad and tested again today.
Then I think I completely understand this shared function. 
Table 17-1, 17-2 and 17-3 are correct and these explain this function well.

I made the below MMUX mapping diagram from these tables.
There are 4 pins, A1_IN11/A2_IN17/A1_IN13/A1_IN15, that can be shared with all PGA0/1/2.
I tested 2 cases, A1_IN13 and A1_IN15, both worked well.

Regards,
Oba