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Original question:

AM261-SOM-EVM: Am261x LP: Profinet device demo issues.

AM261-SOM-EVM: AM2612: RL2 caching with XIP after SW reset.

Vasil Hristev
Prodigy 70 points

Part Number: AM261-SOM-EVM
Other Parts Discussed in Thread: SYSCONFIG

Hello!

I am building an application based on the TI Am261x Industrial communication SDK (2025.00.00). In it I have to have XIP. I configured the XIP based on the "Hello world XIP" example and everything is working as exepected.

Next I decided to include RL2 caching to ensure faster code execution. It is working as well, but only after a power on reset. If my SW resets (due to assert or other problem), I am stuck in RL2_configure  in CSL_RL2_OF_R5FSS0_CORE0_L2_STS_OK_TO_GO_MASK);  I assume that this is to be expected, because after such reset the RL2 block keeps its previous state and there is no OK_TO_GO transition. Am I correct? If so, what is the typical handling in such situations? It is a valid case for us that we may have a SW reset (without power off/on) in production and the SW should not be stuck in this case. Should I do something for RL2 deinit after start?

And a side question. I am using TCMB RAM for caching, because I though that this will achieve the highest performance. Is it OK, or just OCRAM should be used for caching.

Best regards!

  • 0
    TI__Mastermind 22502 points

    HI Vasil,

    Let me discuss this internally and get back with a response. 

    Regards,
    Shaunak

  • 0
    TI__Mastermind 22502 points
    Vasil Hristev said:
    Next I decided to include RL2 caching to ensure faster code execution. It is working as well

    Glad to know this.

    Vasil Hristev said:
    If my SW resets (due to assert or other problem), I am stuck in RL2_configure  in CSL_RL2_OF_R5FSS0_CORE0_L2_STS_OK_TO_GO_MASK);  I assume that this is to be expected, because after such reset the RL2 block keeps its previous state and there is no OK_TO_GO transition. Am I correct?

    Yes, this is expected since after a Software Reset, the RL2 regs will maintain their values. SW reset will not reset the IP or the IP registers.

    Vasil Hristev said:
    If so, what is the typical handling in such situations? I

    What we could do here is:

    1. After a software reset, incase you want to retain the configs, just check the register if RL2_L2_STS is already configured, if yes, do not call the RL2_Configure API. If you are using sysconfig, then modify the rl2_open_close_config.c.xdt file to add this check in Drivers_Rl2Open() function.

    2. If your application can detect that a software reset had occurred, you can reset the RL2_L2_CTRL Register.

    Vasil Hristev said:

    And a side question. I am using TCMB RAM for caching, because I though that this will achieve the highest performance. Is it OK, or just OCRAM should be used for caching.

    The performance for RL2 caching is the same for both TCM and OCRAM. TCM access is 0 wait state from CPU perspective, but from RL2 block, both would pretty much have the same access times.

    Regards,
    Shaunak

  • 0 in reply to Shaunak Deshpande
    Prodigy 70 points

    Hi Shaunak!

    Thanks for your response! I'l try this today and will let you know of the result.

    Best regards!