AM13E23019: Event Trigger Submodule usage for Shadow Load Event for CMPx in MCPWM

Your assessment is correct — the MCPWM Event Trigger Submodule does not provide equivalent functionality to the STM32G4 Repetition Counter for controlling shadow register loading intervals.

Where the ET Submodule Does Have Repetition-Like Behavior

The Event Trigger (ET) Submodule does include a prescaling mechanism via the Event-Trigger Pre-Scale Register (ETPS), which can generate a trigger after every 2nd through 15th occurrence of a source event [1][2]. This is superficially similar to the STM32G4 Repetition Counter in structure.

However, this prescaling capability is strictly scoped to two outputs:

• Interrupt request generation
• ADC Start-of-Conversion (SOC) triggers

It has no influence over shadow register loading for the compare registers (the CCRx equivalents in MCPWM).

How Shadow Loading Actually Works in MCPWM

Shadow register loading for the counter-compare registers (PWMx_CMPA, PWMx_CMPB, CMPC, CMPD) is governed by the CMPCTL[PWMx_LOADAMODE] / CMPCTL[PWMx_LOADBMODE] register bits, and is limited to three fixed hardware events:

There is no hardware mechanism to skip loading cycles — you cannot configure shadow loading to occur at every 2nd, 3rd, or 4th counter event as the STM32G4 Repetition Counter enables.

What About Global Load Mode?

The Global Shadow-to-Active Load Control Register (GLDCTL) does allow synchronizing shadow-to-active transfers across multiple registers simultaneously, but it still ties the load event to the same fixed counter events (zero, period, etc.) — there is no repetition counter mechanism within it either.

It's also worth noting that MCPWM shadow registers have separate memory-mapped addresses for shadow vs. active registers, giving you direct write control. However, writes to the active register are blocked when the register is configured to load from shadow, so you cannot bypass the hardware load event timing through direct writes.

Workaround: Software-Controlled Shadow Updates

Since the hardware doesn't support variable-interval shadow loading natively, the practical workaround is to use the ET Submodule's prescaled interrupt (e.g., fire every 3rd counter zero event) and then manually write to the shadow register inside the ISR only when an update is intended. This effectively replicates the STM32G4 behavior in software:

1. Configure ETPS to prescale interrupts at your desired interval (up to every 15th event) [2]
2. In the ISR, write the new compare value to the shadow register address
3. The shadow-to-active transfer still occurs at the next CTR = Zero or CTR = PRD event, but since you only wrote a new value at the prescaled interval, the effective update rate is controlled

The key trade-off here is latency and determinism — whether this is acceptable depends on your PWM switching frequency and how tight the timing requirements are for your control loop update rate.

If you can share more about the application (e.g., motor control phase, interleaved converter), it may be worth exploring whether DMA-triggered register writes could provide a more deterministic alternative to ISR-based updates.

Citation Index

1. AM13x MCPWM Academy - TI Resource Explorer
2. TI SPRUJF2 - Technical Reference Manual (MCPWM/EPWM)
3. TI SPRUJD3A - Technical Reference Manual (Compare/Shadow Registers)
4. TI SPRADL7 - MCPWM Application Note