• State
  • Locked Locked
  • Replies 5 replies
  • Subscribers 34 subscribers
  • Views 250 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM2434: AM243X DDR ECC test error

liang luo
Prodigy 220 points

Part Number: AM2434
Other Parts Discussed in Thread: SYSCONFIG

Hi experts:

We used the AM2434 EVM Demo board to test the DDR ECC function, wanted to test whether all DDR addresses could be successfully injected and interrupts could be generated.

Env:

SDK version: 11.1.0.17

CCS: 12.8.1

 

We made some changes based on the routine ddr_ecc_test_main_esm_am243x-evm_r5fss0-0_nortos_ti-arm-clang

  1. sysconfig:

  1. ddr_ecc_test.c

See the source code file: ddr_ecc_test.c

ddr_ecc_test.c 

 

Question 1:

The problem encountered is that we can trigger ECC normally from 0x8000_0000 to 0x8000_0007

Exception 0x8000_0008 to 0x8000_0001F

0x8000_0020 to 0x8000_00027 return to normal. The subsequent addresses follow the same pattern.

 

Debugging findings: When injected into the address 0 x8000_0000 ~ 0 x8000_0001f, ECCErrorInfo. SinglebitErrorAddress value is always 0, singlebitErrorCount becomes 1, This 8-byte alignment judgment will affect the results from 0x8000_0008 to 0x8000_001F. Does this judgment not take all scenarios into account? How can it be modified?

 

Question 2:
What is the way ECC data is stored? Is 64 bytes of ECC data generated for every 512 bytes? Or generate 1Byte of data for every 8 bytes? Is ECC data stored right next to DDR data or at the end of the DDR space?

  • 0
    TI__Mastermind 27966 points

    Hi,

    liang luo said:
    What is the way ECC data is stored? Is 64 bytes of ECC data generated for every 512 bytes?

    For every 512 bytes of data, 64 bytes of ECC values are stored immediately after the data. It is similar to the image below with 256 and 32 replaced by 512 and 64 for AM243x.

    However, for the SoC, the DDR data still looks consecutive. Please check the screenshot attached from AM243x TRM below:

    Regards,

    Nihar Potturu

  • 0 in reply to Nihar Potturu
    Prodigy 20 points
    liang luo said:

    Question 1:

    The problem encountered is that we can trigger ECC normally from 0x8000_0000 to 0x8000_0007

    Exception 0x8000_0008 to 0x8000_0001F

    0x8000_0020 to 0x8000_00027 return to normal. The subsequent addresses follow the same pattern.

     Thank you very much for your reply to question 2. What about question 1?

  • 0 in reply to Nihar Potturu
    Prodigy 180 points

    Hi Nihar,

    Question 1:

    The problem encountered is that we can trigger ECC normally from 0x8000_0000 to 0x8000_0007

    Exception 0x8000_0008 to 0x8000_0001F

    0x8000_0020 to 0x8000_00027 return to normal. The subsequent addresses follow the same pattern.

      

    Debugging findings:

    When injected into the address 0 x8000_0000 ~ 0 x8000_0001f, ECCErrorInfo. SinglebitErrorAddress value is always 0, singlebitErrorCount becomes 1, This 8-byte alignment judgment will affect the results from 0x8000_0008 to 0x8000_001F.

    Does this judgment not take all scenarios into account? How can it be modified?

  • 0 in reply to Kelven Huai
    Prodigy 220 points

    I think the reason is that there is a bug here: each bit in the register corresponds to 8 bytes, so it should be "* 8" (or "<< 3u") instead of  "<< 1u".

  • 0 in reply to Nihar Potturu
    TI__Mastermind 30502 points

    Hi Nihar,

    Customer changed it to <<3 and get right result. Please help to confirm, if it is right, suggest file a jira to update in next release.