AM2634-Q1: cache setting for TCM

Fan_Zhang

Part Number: AM2634-Q1
Other Parts Discussed in Thread: AM2634

Hi, experts,

In examples in AM2634 SDK, TCM is set to cached in MPU settings, as shown below.

In the block diagram in TRM, it is shown as below. TCM, as tightly coupled memory, is not accessed through caches, that it should not be set to cached in MPU.

Please help to explain why TCM is set to cached in SDK examples. Thanks.

1 month ago

0 Nilabh Anand 1 month ago

TI__Guru 57110 points

Hi Fan, MPU setting configuration has nothing to do with the actual cache location.

Mpu configuration rather defines how r5f should treat the behaviour of memory

0 Fan_Zhang 1 month ago in reply to Nilabh Anand

TI__Expert 4470 points

Hi, Nilabh,

The question is not about location of cache, but the attribute settings to TCM region.

As shown in screenshot in my previous post, in examples in SDK, Region attribute settings to MPU_REGION1 and MPU_REGION2 are Cached. While MPU_REGION1 and MPU_REGION2 are for TCMA_RAM and TCMB_RAM, that they should not be configurated to Cached, as R5F access TCM without iCache and dCache.

Can you help to check and explain.

Thanks.

0 Nilabh Anand 1 month ago in reply to Fan_Zhang

TI__Guru 57110 points

Hi Fan,

Understood, your point.

you are right, TCM should not be marked as cache.

If marked it causes unnecessary access to L1 cache while doing writes, even though there is no actual cache memory in the bus path.

I will rasie a ticket for this to be corrected in next release.

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AM2634-Q1: cache setting for TCM