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AM263P4-Q1: About Memory Cyclic Redundancy Check (MCRC)

Part Number: AM263P4-Q1

This question is a follow-up to the response we received on the E2E thread below.

(6) AM263P4-Q1: About Memory Cyclic Redundancy Check (MCRC) - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

I have reviewed the sample code. Could you please provide more specific implementation details?
I am attempting to calculate the CRC using the following specifications:

CRC Type: CRC32 (Supports standard CRC-32 (IEEE 802.3))
Seed Value: 0xEDB88320
Data Size Unit: 8 bits (byte-by-byte processing)
Initial Value: 0xFFFFFFFF
Final Processing: XOR the final value with 0xFFFFFFFF (i.e., output inversion)

I believe the seed value can be set using SDL_MCRC_setPSASeedSig().
When using Semi-CPU mode or Auto mode, are there ways to set the data size unit, the initial value, and invert the final value using the SDK (MCRC)?

Regards,

Imaoka

  • Imaoka,

    Before diving into the implementation details, I want to flag an important clarification about your parameters. The value 0xEDB88320 is the reflected polynomial for CRC-32 (IEEE 802.3), not a seed/initial value. The standard CRC-32 initial value is 0xFFFFFFFF (which you also list separately). The MCRC hardware uses a fixed polynomial selected by the CRC type setting — you don't configure the polynomial via the seed register. I'll address your questions assuming you want standard IEEE 802.3 CRC-32 behavior.


    What the SDK Supports via APIs

    The SDL_MCRC_Config_t structure and associated APIs give you control over several parameters in both Semi-CPU and Auto modes [1][2]:

    typedef struct SDL_MCRC_Config_s
    {
        SDL_MCRC_Type_t      type;        // CRC type selection
        SDL_MCRC_DataLength_t dataLen;    // Data width
        SDL_MCRC_DataBitSize  dataBitSize;// Input data size (8, 16, 32, 64-bit)
        SDL_MCRC_BitSwap_t    bitSwap;   // Bit ordering (MSB/LSB)
        SDL_MCRC_ByteSwap_t   byteSwap;  // Byte swap enable/disable
    } SDL_MCRC_Config_t;

    1. Data Size Unit (8-bit / byte-by-byte) — White check mark Supported

    Set dataBitSize to SDL_MCRC_DATA_8_BIT in the configuration structure [3]:

    SDL_MCRC_Config_t mcrcConfig = {
        .type        = SDL_MCRC_TYPE_32BIT,
        .dataLen     = SDL_MCRC_DATALENGTH_32BIT,
        .dataBitSize = SDL_MCRC_DATA_8_BIT,    // byte-by-byte processing
        .bitSwap     = SDL_MCRC_BITSWAP_MSB,
        .byteSwap    = SDL_MCRC_BYTESWAP_ENABLE
    };
    SDL_MCRC_addConfig(instance, channel, &mcrcConfig);

    Important caveat: Although you can specify 8-bit data patterns, the data written to the PSA register is always 64 bits wide internally — patterns smaller than 64 bits are zero-padded [4]. This means the resulting signature will differ from a pure software CRC-32 byte-by-byte calculation. You will need to verify that the output matches your expected IEEE 802.3 results with your specific data.

    2. Initial Value (0xFFFFFFFF) — White check mark Supported via Seed

    Use SDL_MCRC_setPSASeedSig() to set the initial value [5]:

    SDL_MCRC_Signature_t seedValue;
    seedValue.regL = 0xFFFFFFFFU;  // Lower 32 bits
    seedValue.regH = 0xFFFFFFFFU;  // Upper 32 bits (64-bit PSA register)
    
    SDL_MCRC_setPSASeedSig(instance, channel, &seedValue);

    This sets the PSA register's starting state before CRC computation begins.

    3. Final XOR Inversion (XOR with 0xFFFFFFFF) — X Not Supported in Hardware

    The MCRC hardware does not natively support final XOR inversion of the output signature [6]. You must perform this step in software after retrieving the computed signature:

    SDL_MCRC_Signature_t resultSig;
    SDL_MCRC_getPSASectorSig(instance, channel, &resultSig);
    
    // Apply final XOR inversion in software
    uint32_t finalCRC = resultSig.regL ^ 0xFFFFFFFFU;

    In Semi-CPU mode, you read the signature from the PSA Sector Signature Registers and apply the XOR yourself [7]. In Auto mode, the hardware compares the signature against a pre-stored reference value — so you would need to store the pre-inverted expected CRC in the CRC Value Register to account for the missing final XOR step [7].


    Recommended Programming Sequence

    For Semi-CPU mode [8]:

    1. SDL_MCRC_channelReset(instance, channel)
    2. SDL_MCRC_init(instance, channel, watchdogPreload, blockPreload)
    3. SDL_MCRC_config(instance, channel, patternCount, sectorCount, SDL_MCRC_OPERATION_MODE_SEMICPU)
    4. SDL_MCRC_addConfig(instance, channel, &mcrcConfig)
    5. SDL_MCRC_setPSASeedSig(instance, channel, &seedValue)
    6. Transfer data via DMA to PSA signature register
    7. SDL_MCRC_getPSASectorSig(instance, channel, &resultSig)
    8. Apply resultSig.regL ^= 0xFFFFFFFF in software

    Open Items to Verify

    • Bit/byte swap settings: Achieving IEEE 802.3-compliant output may require specific combinations of bitSwap and byteSwap. The standard CRC-32 involves bit-reversal of input bytes, which the SDL_MCRC_BITSWAP_LSB setting may address — but this needs empirical verification against known test vectors.
    • 64-bit zero-padding impact: Since 8-bit data is padded to 64 bits internally, confirm the computed signature matches your reference implementation with a known data set before relying on it in production.

    I'd recommend running a simple test with a known input (e.g., the ASCII string "123456789" which should yield CRC-32 = 0xCBF43926) to validate your configuration.


    1. SDL MCRC Header Source
    2. SDL MCRC API Guide
    3. SDL MCRC Header - DataBitSize Enum
    4. SDL MCRC API - PSA Register Padding
    5. SDL MCRC API - setPSASeedSig
    6. AM263PX TRM - MCRC Module
    7. AM263PX TRM - Semi-CPU and Auto Mode
    8. SDL MCRC Example Page

    Best Regards,

    Zackary Fleenor

  • Hi Zackary,

    This issue has been resolved. Thank you very much for your assistance.
    Regards, Imaoka