Parity check for ADC

Vaclav Cechticky

Hello,

I'm trying reproduce/re-run available tests which are creating and verifying parity errors for ADC1 and ADC2 on RM48 HDK.

Whereas other provided parity tests are working in a predictable way, the parity checks for ADC1,2 are sometimes passed, one is failed or both failed.

I guess that I missed some configuration step, or has anybody other explanation for such effect?

Thank you

Vaclav

over 13 years ago

0 Sunil Oak over 13 years ago

TI__Mastermind 49120 points

Hello Vaclav,

The ADC also supports a special mode called the RAM test mode. This mode can be enabled via bit 16 (RAM TEST EN) of the ADC Operating Mode Control Register (ADOPMODECR). When this bit is set, the ADC results' memory including the parity bit becomes writable by the CPU (and other bus masters). Please make sure that this bit is not being set by the application when it is running the ADC RAM parity error detection mechanism.

Regards, Sunil

0 Vaclav Cechticky over 13 years ago in reply to Sunil Oak

Intellectual 560 points

Hello Sunil,

It's working now. Also the section 18.9.3 from SPNU499 helped me to get it running.

Thank you

Vaclav

0 Sunil Oak over 13 years ago in reply to Vaclav Cechticky

TI__Mastermind 49120 points

Hello Vaclav,

Thanks for the confirmation. Is there anything incorrect in the parity detection test mechanism for ADC RAMs in the example initialization code (SPNA106)?

Regards, Sunil

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Parity check for ADC