Part Number: MSPM0G1519
Hello,
What's the minimum active time that is required for the wake signal to be asserted before the level is latched in IOMUX to wake the MCU?
IE if I have a GPIO PA0 configured for wake, active low, how long does the line need to be pulled low for for the MCU to be woken up?
It looks like all the numbers in the datasheet relate to time from the pin is asserted to when the device starts running code:
Munan
Hi Munan,
What's the minimum active time that is required for the wake signal to be asserted before the level is latched in IOMUX to wake the MCU?
This is recorded in the TRM below how GPIO event generated:
The input signal should at least larger than 1 ULPCLK to be captured by first synchronizer
And the transfer time is two ULPCLK cycles (two Synchronizers).
So, the max delay time (compared to the GPIO PIN edge) is three ULPCLK cycles.
B.R.
Sal
