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AM2612: AM2612 FSITX timing characteristics

Billy Zhao
Prodigy 40 points

Part Number: AM2612

Hi Team,

 

In my design I connect the am2612 MCU to a FPGA via the FSI interface. I am doing the timing analysis to see how much setup time and hold time I can have. But the timing characteristics of FSI TX is not clear to me. 

  • Is FSIT2 the actual measured value in the pad?
  • Is FSIT3 is measured related to the ideal internal FSI TX clock inside the MCU or it is actually related to the actual FSITX_CLK output waveform, whose duty‑cycle distortion is already captured by FSIT2?

image.png

Thank you in advance for your help,

Y.Zhao

  • +1
    TI__Mastermind 32063 points

    Hi Y.Zhao,

    FSIT2 — Yes, it is measured at the pad

    FSIT2 specifies the pulse width of the actual FSITX_CLK output (both high and low phases), defined as 0.5P ± 1 ns (where P is the clock period) [1]. This captures the real duty-cycle distortion present on the physical clock signal at the device pad.

    FSIT3 — Measured relative to the actual FSITX_CLK output, not an ideal internal clock

    FSIT3 is the delay from the actual FSITX_CLK edge (rising or falling) to when FSITX_Dx data becomes valid, specified as 0.25P ± 2 ns [1]. The timing diagram (Figure 6-24 in the datasheet) confirms that FSIT3 is measured from the real transitions of the output clock waveform — not from an idealized internal reference [1].

    This means the duty-cycle distortion captured by FSIT2 is already reflected in the FSIT3 measurement. You do not need to separately derate FSIT3 for duty-cycle effects when building your timing budget.

    Practical implication for your FPGA timing analysis

    For your setup/hold analysis at the FPGA receiver, you can directly use:

    Parameter
    What it gives you
    Spec
    FSIT2
    Clock pulse width (duty cycle) at pad
    0.5P ± 1 ns
    FSIT3
    Data valid delay after clock edge at pad
    0.25P ± 2 ns

    From there, add your PCB trace delay skew (clock vs. data) and compare against your FPGA's input setup and hold requirements to determine your timing margin.

    Also note that the AM2612 provides programmable delay compensation (FSIT4–FSIT7) on the TX clock and data lines, which can help you adjust skew if your margins are tight [1]. Each delay element adds 0.3–1 ns of incremental delay [1].

    If you need further help with the complete timing budget calculation, it would be useful to know your target FSI clock frequency and the specific FPGA device/family you're using.

    Resources: AM2612 Datasheet (SPRSPA7C) — FSITX Switching Characteristics, p.122

    Best Regards,

    Zackary Fleenor