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MSPM0L1228: ADC sample speed using internal vref

HS FAE Germany
Mastermind 32760 points

Part Number: MSPM0L1228

Hi,
the d/s mention a max ADC sample speed of 200ksps when using internal vref. Customer needs to sample with 288ksps. What would be the error with this sample speed?
I know the limited factor is Ivref of 1uA. Can a bigger cap improve the max sample speed?
I think the worst case is if the vref cap is complete empty of full.

Regards, Holger

  • 0
    TI__Mastermind 29845 points

    Hi Holger,

    Please use the external Vref in this case.

    The ADC conversion data will be inaccurate with larger error.

    HS FAE Germany said:
    I know the limited factor is Ivref of 1uA.

    Where this limitation spec record? I don't find it in the DS.

    From my understanding, the reason is the VREF is not stable to ADC if ADC sample rate larger than 200ksps.

    B.R.

    Sal

  • 0 in reply to Sal Ye
    TI__Mastermind 32760 points

    Hi Sal,
    I thought that vref buffer cap couldn't charged/discharged due Ivref limited and time limit when converting fast.

    Regards, Holger

  • 0 in reply to HS FAE Germany
    TI__Mastermind 29845 points

    Hi Holger,

    Sal Ye said:
    Where this limitation spec record? I don't find it in the DS.

    Could you remind me of the spec, I want to know where records Ivref is limited to 1uA.

    HS FAE Germany said:
    I thought that vref buffer cap couldn't charged/discharged due

    This is correct.

    HS FAE Germany said:
    due Ivref limited and time limit when converting fast.

    Please suggest me where you find the current limitation. I want to double check the 1uA limitation description with internal team.

    B.R.

    Sal

  • 0 in reply to Sal Ye
    TI__Mastermind 32760 points

    sorry it was 100uA stated in the datasheet:

    but still this is the limited factor, right?

  • 0 in reply to HS FAE Germany
    TI__Mastermind 32760 points

    Hi Sal,
    please comment here on how big the error would be and if you can somehow calculate it.

    Regards, Holger

  • 0 in reply to HS FAE Germany
    TI__Mastermind 29845 points

    Hi Holger,

    The limitation comes from VREF built-in cap, which can not afford the ADC sampling rate over than 200ksps.

    B.R.

    Sal

  • 0 in reply to HS FAE Germany
    TI__Mastermind 29845 points

    Hi Holger,

    We don't recommend use it over than 200ksps. We can not guarantee its error, especially when it comes to corner case.

    B.R.

    Sal

  • 0 in reply to Sal Ye
    TI__Mastermind 32760 points

    Hi Sal,

    can you calculate the error somehow?
    How big is the internal cap, current and resistor.

    Regards, Holger

  • 0 in reply to HS FAE Germany
    TI__Mastermind 29845 points

    Hi Holger,

    Per discussion, the error can not be calculated in certain pattern. The reason is that the missing code might happen if the sampling rate over the limitation. If missing code happens in High address, then the error will be large.

    For examples:
    Expected ADC result:1101.0000.0001b -> Real ADC result with code missing when ADC sample rate is too fast:1100.0000.0001b

    Now i get some comments from internal team that the design spec might support higher rate but this is not guaranteed by datasheet. Could you please help confirm the customer setting on ADC channels:

    adc clock source & clock divider

    sample time

    resolution (equals to conversion time)

    If all the ADC init code or setting can be shared will be better.

    B.R.

    Sal

  • 0 in reply to Sal Ye
    TI__Mastermind 32760 points

    Hi Sal,
    they use the ULPCLK with 1 clock divider and a sample window (SCOMPx) with 143.

    Regards, Holger

  • 0 in reply to HS FAE Germany
    TI__Mastermind 29845 points

    Hi Holger,

    With this configuration, the sample time is 143/32MHz=4.46875us. How does customer achieve 288ksps?

    B.R.

    Sal

  • 0 in reply to Sal Ye
    TI__Mastermind 29845 points

    Hi Holger,

    After confirmed with internal team, if users select internal reference mode for ADC, we will automatically limits the CONVCLK to smaller than 4MHz. Then the VREF will be good for ADC sampling.

    So, users don't need take the VREF setting time when using VREF with ADC. The overall sampling rate is automatically limited by ADC internal clock process.

    B.R.

    Sal

  • 0 in reply to Sal Ye
    TI__Mastermind 32760 points

    Hi Sal,
    sorry this was already the modification for 200ksps. For 288ksps they used:
    ADC Clock Source:       ULPCLK, Divider: 1
    Hardware-Averaging: 8x
    SCOMP0:                           75 Clock Cycles
    Resolution:                       12-bit
    Due to the many channels, we change the configuration to ULLMEM.MEMCTL after half (9) and adjust the DMA transmission. It disables the ADC for a moment and we lose some time.
    Unfortunately, there are only MEMRES0 to MEMRES11 instead of MEMRES23 as described in the register description of the CTL2 register in the reference manual. Here, the number of MEMRESx registers varies several times within the document.

    Rgs, Holger