MSPM0L1228: ADC sample speed using internal vref

HS FAE Germany

Part Number: MSPM0L1228
Other Parts Discussed in Thread: LP-MSPM0L2228

Hi,
the d/s mention a max ADC sample speed of 200ksps when using internal vref. Customer needs to sample with 288ksps. What would be the error with this sample speed?
I know the limited factor is Ivref of 1uA. Can a bigger cap improve the max sample speed?
I think the worst case is if the vref cap is complete empty of full.

Regards, Holger

2 months ago

0 Sal Ye 2 months ago

TI__Mastermind 31095 points

Hi Holger,

Please use the external Vref in this case.

The ADC conversion data will be inaccurate with larger error.

HS FAE Germany said:
I know the limited factor is Ivref of 1uA.

Where this limitation spec record? I don't find it in the DS.

From my understanding, the reason is the VREF is not stable to ADC if ADC sample rate larger than 200ksps.

B.R.

Sal

0 HS FAE Germany 2 months ago in reply to Sal Ye

TI__Mastermind 32850 points

Hi Sal,
I thought that vref buffer cap couldn't charged/discharged due Ivref limited and time limit when converting fast.

Regards, Holger

0 Sal Ye 2 months ago in reply to HS FAE Germany

TI__Mastermind 31095 points

Hi Holger,

Sal Ye said:
Where this limitation spec record? I don't find it in the DS.

Could you remind me of the spec, I want to know where records Ivref is limited to 1uA.

HS FAE Germany said:
I thought that vref buffer cap couldn't charged/discharged due

This is correct.

HS FAE Germany said:
due Ivref limited and time limit when converting fast.

Please suggest me where you find the current limitation. I want to double check the 1uA limitation description with internal team.

B.R.

Sal

0 HS FAE Germany 2 months ago in reply to Sal Ye

TI__Mastermind 32850 points

sorry it was 100uA stated in the datasheet:

but still this is the limited factor, right?

0 HS FAE Germany 2 months ago in reply to HS FAE Germany

TI__Mastermind 32850 points

Hi Sal,
please comment here on how big the error would be and if you can somehow calculate it.

Regards, Holger

0 Sal Ye 2 months ago in reply to HS FAE Germany

TI__Mastermind 31095 points

Hi Holger,

The limitation comes from VREF built-in cap, which can not afford the ADC sampling rate over than 200ksps.

B.R.

Sal

0 Sal Ye 2 months ago in reply to HS FAE Germany

TI__Mastermind 31095 points

Hi Holger,

We don't recommend use it over than 200ksps. We can not guarantee its error, especially when it comes to corner case.

B.R.

Sal

0 HS FAE Germany 2 months ago in reply to Sal Ye

TI__Mastermind 32850 points

Hi Sal,

can you calculate the error somehow?
How big is the internal cap, current and resistor.

Regards, Holger

0 Sal Ye 1 month ago in reply to HS FAE Germany

TI__Mastermind 31095 points

Hi Holger,

Per discussion, the error can not be calculated in certain pattern. The reason is that the missing code might happen if the sampling rate over the limitation. If missing code happens in High address, then the error will be large.

For examples:
Expected ADC result:1101.0000.0001b -> Real ADC result with code missing when ADC sample rate is too fast:1100.0000.0001b

Now i get some comments from internal team that the design spec might support higher rate but this is not guaranteed by datasheet. Could you please help confirm the customer setting on ADC channels:

adc clock source & clock divider

sample time

resolution (equals to conversion time)

If all the ADC init code or setting can be shared will be better.

B.R.

Sal

0 HS FAE Germany 1 month ago in reply to Sal Ye

TI__Mastermind 32850 points

Hi Sal,
they use the ULPCLK with 1 clock divider and a sample window (SCOMPx) with 143.

Regards, Holger

0 Sal Ye 1 month ago in reply to HS FAE Germany

TI__Mastermind 31095 points

Hi Holger,

With this configuration, the sample time is 143/32MHz=4.46875us. How does customer achieve 288ksps?

B.R.

Sal

0 Sal Ye 1 month ago in reply to Sal Ye

TI__Mastermind 31095 points

Hi Holger,

After confirmed with internal team, if users select internal reference mode for ADC, we will automatically limits the CONVCLK to smaller than 4MHz. Then the VREF will be good for ADC sampling.

So, users don't need take the VREF setting time when using VREF with ADC. The overall sampling rate is automatically limited by ADC internal clock process.

B.R.

Sal

0 HS FAE Germany 1 month ago in reply to Sal Ye

TI__Mastermind 32850 points

Hi Sal,
sorry this was already the modification for 200ksps. For 288ksps they used:
ADC Clock Source:       ULPCLK, Divider: 1
Hardware-Averaging: 8x
SCOMP0:                           75 Clock Cycles
Resolution:                       12-bit
Due to the many channels, we change the configuration to ULLMEM.MEMCTL after half (9) and adjust the DMA transmission. It disables the ADC for a moment and we lose some time.
Unfortunately, there are only MEMRES0 to MEMRES11 instead of MEMRES23 as described in the register description of the CTL2 register in the reference manual. Here, the number of MEMRESx registers varies several times within the document.

Rgs, Holger

0 HS FAE Germany 1 month ago in reply to Sal Ye

TI__Mastermind 32850 points

Hi Sal,

That's interesting.However, their measurements show that the CONVCLK apparently runs at 32 MHz. CLKFREQ.FRANGE is definitely set to 5 (>24 to 32 MHz / divide by 8) and VRSEL is set to 2h (internal reference). What could be the reason?

With the current settings, however, it works well. In fact, if the CONVCLK needs to run at 4 MHz, they would have to either adjust the input filter or in the worst case go to an external reference or the MSPM0G1228.

ADCCLK used for both sampling and conversion -> sourced from 32MHz ULPCLK
t_sync= 0, since ULPCLK is used
Sample window:
- Generated with SAMPCLK, sourced from ADCCLK using SCLKDIV (is set to 0 -> Do not divide/divide by 1) -> 32MHz
- SCOMP0 VAL is set to 146. -> number of sample clocks = VAL x SCLKDIV -> still 146 clock cycles
Conversion window:
- Generated with CONVCLK, sourced from ADCCLK using VRSEL and CLKFREQ -> The CONVCLK frequency is not to exceed 4MHz when using the internal VREF. Since the ADCCLK is set to 32 MHz, CLKFREQ.FRANGE is set to 5 (>24 to 32 MHz), which applies the :8 divider, according to Figure 15-2, generating those 4 MHz.
Overall time:
- Sample window: 146 clock cycles @ 32 MHz
- Conversion window: 14 clock cycles @ 4 MHz -> 14*8 = 112 clock cycles @ 32 MHz
- Overall: 146+112 = 258 clock cycles @ 32 MHz -> 8.06 us -> 03 ksps
- 4-Oversampling -> 8.06 *4 = 32.25 us
- 9 Channels: 32.25*9 = 3 us

However, I am measuring 2 us, which matches with the following calculation, assuming a CONVCLK of 32 MHz:
- Sample window: 146 clock cycles @ 32 MHz
- Conversion window: 14 clock cycles @ 32 MHz
- Overall: 146+14 = 160 clock cycles @ 32 MHz -> 5.00 us -> 200 ksps
- 4-Oversampling -> 5.00*4 = 20.00 us
- 9 Channels: 20.00 *9 = 00 us

Regards, Holger

0 Sal Ye 1 month ago in reply to HS FAE Germany

TI__Mastermind 31095 points

Hi Holger:

Please ask customer for double check, I tested LP-MSPM0L2228 which match TRM description.

Test code:

    while (1) {
        /* Low - High pulse represents sample+conversion time */
        /* 4 channel sampling:
         * Sample time = 1us
         * CONV time = 14* 1/4M = 3.5us (12-bit, 4MHz with internal clock; ulpclk/8=4MHz)
         * Total time per channel: 4.5us
         *
         * Total time for 4 channels: 4.5us*4=18us
         *
         * RIS assert time = 1/4M = 0.25us
         * Total time: 18.25us+ minus time (CPU write register time)
         * */
        DL_GPIO_clearPins(GPIO_LEDS_PORT, GPIO_LEDS_USER_LED_1_PIN);
        __NOP();
        DL_ADC12_startConversion(ADC12_0_INST);
        while(DL_ADC12_INTERRUPT_MEM3_RESULT_LOADED !=
                DL_ADC12_getRawInterruptStatus(ADC12_0_INST, DL_ADC12_INTERRUPT_MEM3_RESULT_LOADED));
        DL_GPIO_setPins(GPIO_LEDS_PORT, GPIO_LEDS_USER_LED_1_PIN);
        __NOP();

//        gCheckADC = false;
//        adcResult = DL_ADC12_getMemResult(ADC12_0_INST, DL_ADC12_MEM_IDX_0);

        DL_ADC12_clearInterruptStatus(ADC12_0_INST, DL_ADC12_INTERRUPT_MEM3_RESULT_LOADED);
        DL_ADC12_enableConversions(ADC12_0_INST);
        __NOP();
    }

Test result:

B.R.

Sal

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MSPM0L1228: ADC sample speed using internal vref