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RM48L952: RAM Diagnostics: Dual port PBIST Diagnostic test failing

Muhammad Ahtasham Baig
Prodigy 10 points

Part Number: RM48L952
Other Parts Discussed in Thread: HALCOGEN,

Dear Team,

I am going through some problem, I want to verify because it is also occuring in code generated via Halcogen in sys_startup.c as well. my main goal is bring ram related test code in seperate module.

Below I am attach code snippet:

#define RAM_DIAG_DP_PBIST_RINFOL                                               \
  ((uint32)0x00000000U   /* EMAC RAM */                                        \
   | (uint32)0x00000000U /* USB RAM */                                         \
   | (uint32)0x00000800U /* DMA RAM */                                         \
   | (uint32)0x00000200U /* VIM RAM */                                         \
   /* | (uint32)0x00000040U MIBSPI1 RAM (not ORed into mask) */                 \
   /* | (uint32)0x00000080U MIBSPI3 RAM (not ORed into mask) */                 \
   /* | (uint32)0x00000100U MIBSPI5 RAM (not ORed into mask) */                 \
   | (uint32)0x00000004U /* CAN1 RAM */                                        \
   /* | (uint32)0x00000008U CAN2 RAM (not ORed into mask) */                     \
   /* | (uint32)0x00000010U CAN3 RAM (not ORed into mask) */                     \
   /* | (uint32)0x00000400U ADC1 RAM (not ORed into mask) */                    \
   | (uint32)0x00020000U /* ADC2 RAM */                                        \
   /* | (uint32)0x00001000U HET1 RAM (not ORed into mask) */                    \
   /* | (uint32)0x00040000U HET2 RAM (not ORed into mask) */                    \
   /* | (uint32)0x00002000U HTU1 RAM (not ORed into mask) */                    \
   | (uint32)0x00080000U /* HTU2 RAM */                                        \
   | (uint32)0x00004000U /* RTP RAM */                                         \
   | (uint32)0x00000000U /* FRAY RAM */)

#define RAM_DIAG_DP_PBIST_ALGO                                                 \
  ((uint32)PBIST_March13N_DP   /* 0x004 */                                     \
   | (uint32)PBIST_DOWN1a_DP   /* 0x010 */                                     \
   | (uint32)PBIST_MapColumn_DP) /* 0x040 — total 0x054 */

/** Phase 2: dual-port PBIST + checkRAMECC (runs concurrently while PBIST
    *  operates on peripheral RAMs — TRM §7.6.1 and §7.6.2 sequence).
    *  ALGO = RAM_DIAG_DP_PBIST_ALGO (0x054): March13N_DP | Down1A_DP |
    *  MapColumn_DP. MapColumn_DP is mandatory for two-port RAMs. */


   static void ram_diag_phase_dp_pbist_ecc(void) {
     pbistRun(RAM_DIAG_DP_PBIST_RINFOL, RAM_DIAG_DP_PBIST_ALGO);

     checkRAMECC();

     /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
     while (pbistIsTestCompleted() != TRUE) {
     } /* Wait */

     if (pbistIsTestPassed() != TRUE) {
       /* Capture diagnostic registers BEFORE pbistFail() — pbistFail() may
        * never return (calls memoryPort0TestFailNotification which may loop).
        * Snapshot is stored in s_pbist_fail_snapshot; readable under debugger.
        * RGS = s_pbist_fail_snapshot.ramt >> 24 identifies the failing RAM group. */
       ram_diag_pbist_registers_read(&s_pbist_fail_snapshot.fsrf0,
                                     &s_pbist_fail_snapshot.ramt);
       pbistFail();
     }

     pbistStop();
   }

Inside the macro for RAM_DIAG_DP_PBIST_RINFOL, when i enable any of the peripheral's memory offset it gets failed otherwise passes with current configuration. I want to mention that all the peripherals are enabled from halcogen already. Please let me know if there is any specific solution we need to implement or is it known problem.

Regards

  • 0
    TI__Guru* 80016 points

    Hi Muhammad,

    Our internal AI suggesting some important things that might we missed, so on the first phase could you please verify them once

    You're experiencing failures during RAM testing with the PBIST (Programmable Built-in Self Test) module when you enable certain peripheral RAM regions in the RAM_DIAG_DP_PBIST_RINFOL macro. This issue occurs even in Halcogen-generated code.

    Root Cause Analysis

    The issue is likely related to one of these common causes:

    1. Peripheral Initialization Sequence: Some peripheral RAMs need to be properly initialized before running PBIST tests.

    2. Clock Configuration: Certain peripheral RAMs require their respective peripheral clocks to be enabled before testing.

    3. Power Domain Issues: Some peripherals might be in a low-power state when the test is run.

    4. Reserved Memory Regions: The TRM may specify certain memory regions that shouldn't be tested with specific algorithms.

    Recommended Solution

    1. Check Peripheral Clock Status

    Ensure that the clocks for all peripherals you want to test are enabled.

    2. Modify Your Test Approach

    Try testing peripheral RAMs in smaller groups rather than all at once.

    3. Check Peripheral Initialization

    Some peripherals need specific initialization before their RAM can be tested.

    4. Consult the TRM

    The RM48L952 TRM may have specific requirements for PBIST testing of peripheral RAMs. Look for sections about:

    • Memory map restrictions
    • Recommended test algorithms for specific memories
    • Initialization requirements before testing

    Additional Considerations

    1. Algorithm Selection: Not all algorithms are suitable for all RAM types. For dual-port RAMs, you're correctly using MapColumn_DP, but verify if each peripheral RAM has specific algorithm requirements.

    2. Error Handling: Your error capture mechanism is good, but consider adding more detailed diagnostics.

    --
    Thanks & regards,
    Jagadish.