Hi Jung,

On the first phase i would suggest you to refer the below response of our internal AI tool, if you have further questions i will again assist you to resolve them.

Handling Large HTU Transfers on RM57L843

You're correct that the IFTCOUNT field is limited to 8 bits (max 255 transfers per frame). Here are the recommended approaches for transferring 2048 words:

1. Multi-Frame Transfer with Control Packet Chaining

The HTU supports control packet chaining which is the hardware mechanism designed for this purpose.

Implementation:

#define MAX_FRAME_SIZE 255
#define TOTAL_WORDS 2048
#define NUM_FRAMES ((TOTAL_WORDS + MAX_FRAME_SIZE - 1) / MAX_FRAME_SIZE) // = 9 frames

void Transmit_Engine_Setup(uint32_t* sourceAddr, uint32_t targetIdx, uint32_t len)
{
    uint32_t remaining = len;
    uint32_t offset = 0;
    uint32_t frameIdx = 0;
    
    // Disable HTU
    htuREG1->GC = 0x00010000;
    for(volatile int i=0; i<3000; i++);
    htuREG1->CPENA = 0x00;
    htuREG1->MPCS = 0x00000005;
    
    // Setup control packets with chaining
    while(remaining > 0)
    {
        uint32_t frameSize = (remaining > MAX_FRAME_SIZE) ? MAX_FRAME_SIZE : remaining;
        
        htuDCP1[frameIdx].IFADDRA = (uint32_t)(sourceAddr + offset);
        htuDCP1[frameIdx].IHADDRCT = (1U << 23) | (1U << 18) | targetIdx;
        htuDCP1[frameIdx].ITCOUNT = (0x00010000) | frameSize;
        
        // Setup chaining: point to next control packet
        if(remaining > MAX_FRAME_SIZE)
        {
            // Enable chaining (bit 20) and set next CP address
            htuDCP1[frameIdx].IHADDRCT |= (1U << 20); // TMBA bit
            htuDCP1[frameIdx].ITCOUNT |= ((frameIdx + 1) << 24); // Next CP index
        }
        
        offset += frameSize;
        remaining -= frameSize;
        frameIdx++;
    }
    
    // Enable HET and HTU
    hetREG1->GCR = 0x00010001;
    hetREG1->REQENS = (1U << 0);
    htuREG1->CPENA = 0x01;
}

2. Interrupt-Driven Approach

If you prefer more control, use HTU interrupts to trigger the next transfer:

volatile uint32_t g_current_offset = 0;
volatile uint32_t g_remaining_words = 0;
volatile uint32_t* g_source_ptr = NULL;

void Transmit_Engine_Setup(uint32_t* sourceAddr, uint32_t targetIdx, uint32_t len)
{
    g_source_ptr = sourceAddr;
    g_current_offset = 0;
    g_remaining_words = len;
    
    htuREG1->GC = 0x00010000;
    for(volatile int i=0; i<3000; i++);
    htuREG1->CPENA = 0x00;
    htuREG1->MPCS = 0x00000005;
    
    // Enable HTU interrupts
    htuREG1->INTENAS = 0x01; // Enable interrupt for CP0
    
    // Start first frame
    Start_Next_Frame(targetIdx);
    
    hetREG1->GCR = 0x00010001;
    hetREG1->REQENS = (1U << 0);
    htuREG1->CPENA = 0x01;
}

void Start_Next_Frame(uint32_t targetIdx)
{
    uint32_t frameSize = (g_remaining_words > MAX_FRAME_SIZE) ? 
                         MAX_FRAME_SIZE : g_remaining_words;
    
    htuDCP1[0].IFADDRA = (uint32_t)(g_source_ptr + g_current_offset);
    htuDCP1[0].IHADDRCT = (1U << 23) | (1U << 18) | targetIdx;
    htuDCP1[0].ITCOUNT = 0x00010000 | frameSize;
}

#pragma INTERRUPT(htuInterrupt, IRQ)
void htuInterrupt(void)
{
    // Check if transfer complete
    if(htuREG1->INTFLG & 0x01)
    {
        htuREG1->INTFLG = 0x01; // Clear flag
        
        g_current_offset += MAX_FRAME_SIZE;
        g_remaining_words -= MAX_FRAME_SIZE;
        
        if(g_remaining_words > 0)
        {
            Start_Next_Frame(HTU_DCP0_TARGET);
        }
        else
        {
            // Transfer complete
            htuREG1->CPENA = 0x00;
        }
    }
}

3. Key Points

• TMBA bit (bit 20 in IHADDRCT): Enables control packet chaining
• NXTCP field (bits 31-24 in ITCOUNT): Specifies next control packet index
• Maximum 16 control packets available per HTU instance
• For 2048 words: need 9 frames (8×255 + 1×8)

Recommendation

Use Method 1 (Control Packet Chaining) as it's hardware-supported and most efficient. The HTU will automatically process all chained packets without CPU intervention.

--
Thanks & Regards,
Jagadish.