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[FAQ] AM13E23019: AM13E230x : Frequently asked ADC questions

Arpit Varahmihir
Prodigy 10 points

Part Number: AM13E23019

  1. What are the most Common ADC Terms and their definitions?
  2. What operations can be performed in the ADC Post-Processing Block in hardware?  
  3. What is the temperature range of operation for the ADC peripheral?
  4. What is the ENOB (Effective Number of Bits) for the AM13E230x ADC? 
  5. Does AM13E230x ADC support burst mode? 
  • 0
    TI__Prodigy 10 points
    Arpit Varahmihir said:
    What are the most Common ADC Terms and their definitions?

    ACQPS (Acquisition Plus Sample Time)

    Defines the length of time the sampling capacitor is connected to the input channel, measured in ADCCLK cycles.

    ADC (Analog-to-Digital Converter)

    A circuit that converts a continuous analog signal (voltage) into a discrete digital representation (numerical value).

    ADCCLK (ADC Clock)

    The clock signal that drives the ADC's internal operations, including sampling and conversion.

    ADCRESULT Registers

    Registers within the ADC module that store the digital output value resulting from a conversion.

    CHSEL (Channel Select)

    A configuration setting within a SOC specifying which input channel (pin or internal signal) the ADC will sample.

    CMPSS

    Comparator Subsystem. Used with the ADC for comparing sampled values against reference voltages.

    CTL (Control)

    Refers to control registers used to configure and manage the ADC module.

    DMA (Direct Memory Access)

    A hardware feature allowing data transfer between peripherals (like the ADC) and memory without CPU intervention.

    DL_ADC

    DriverLib functions for managing the ADC peripheral (e.g., DL_ADC_disableSequencer).

    ENOB (Effective Number of Bits)

    A measure of the ADC’s actual resolution, considering noise and impairments. Higher ENOB indicates greater accuracy.

    ISR (Interrupt Service Routine)

    A function automatically executed by the processor when an interrupt occurs (e.g., upon ADC conversion completion).

    Internal Test Mode

    A hardware feature allowing direct connection of internal analog signals to the ADC input, bypassing external pins.

    PGA (Programmable Gain Amplifier)

    An amplifier increasing the signal strength of weak signals before ADC conversion.

    PPB (Post-Processing Block)

    A hardware block performing signal conditioning/monitoring tasks on ADC data before CPU transfer.

    SDK (Software Development Kit)

    Tools and libraries provided by the chip manufacturer to aid application development.

    SOC (Start of Conversion)

    Represents a single conversion recipe or step within an ADC sequence (SOC0-SOC15).

    SEQ (Sequencer)

    A block within the ADC managing the ordered execution of a series of SOCs.

    SYSCTL (System Control)

    A module controlling system-level peripherals, including clock and power management.

    TRM (Technical Reference Manual)

    A detailed document describing the ADC’s architecture, registers, and functionalities.

    TRIGSEL (Trigger Select)

    A configuration setting specifying the event initiating the conversion sequence (e.g., PWM, Timer, GPIO).

    Oversampling

    Taking multiple samples of the same signal and averaging them to reduce noise and improve accuracy.

    Arpit Varahmihir said:
    What operations can be performed in the ADC Post-Processing Block in hardware?  

    The PPB is designed to offload common signal-conditioning and monitoring tasks directly into hardware—so the CPU doesn’t have to process every ADC sample. Some of the operations supported in PPB are:

    • Offset Correction: Automatically subtracts a programmed offset from ADC result
    • Error Calculation: Computes difference between ADC result and reference value.
    • Limit Detection (High/Low Threshold): Compares ADC result against programmable limits and generates events if result is above upper threshold or below lower threshold.
    • Zero-Crossing Detection:   Detects when signal crosses zero (or reference level) 
    • Sample Delay Capture: Captures timing information related to sampling
    • Oversampling (Averaging):  Combines multiple samples internally and improves noise performance and effective resolution.

     The hardware does not support subtract or complement feature in the AM13E230x ADC hardware, but this limitation can be handled in software.

    Arpit Varahmihir said:
    What is the temperature range of operation for the ADC peripheral?

    The ADC IP itself is designed for a wider range of -40°C to 155°C; however, the device-level temperature range of operation is: -40°C to 125°C junction temperature. Considering the overall integration into the SoC, the overall operation temperatures that should be considered for AM13E230x is -40°C to 125°C.


    Arpit Varahmihir said:
    What is the ENOB (Effective Number of Bits) for the AM13E230x ADC?

     The ENOB for the AM13E230x ADC is 10.8 bits.

    Arpit Varahmihir said:
    Does AM13E230x ADC support burst mode?

    There is no true burst mode on the AM13E230x that performs a pre-programmed number of conversions in sequence. Instead, for each SOC, the number of oversamples can be selected individually. In true burst mode, samples and conversions are both performed; on the AM13E230x, only sampling is performed and the accumulated sum is stored in the post-processing block (PPB) register. Oversampling maps to what is commonly referred to as burst mode — hardware-driven repeated sampling without CPU intervention, often supported through a trigger repeater. In practice, a trigger source is configured, and the ADC takes a programmed number of samples per period, optionally reducing CPU load via DMA or end-of-sequence interrupts.