AM2612: Clarification on XFR2VBUS functionality of PRU-ICSS

Dhruva Kashyap

Part Number: AM2612

Hi team,

I'd like to clarify the XFR2VBUS functionality of the PRU-ICSS on AM2612 MCU.

From the TRM, I gather that there are 2x RX XFR2VBUS accelerators and no TX accelerators in one ICSS instance (fig7-22 of sprujb6b):

However, the text preceding this fig states that "There are two sets of XFR2VBUS for each Slice.", implying 4 XFR2VBUS in total. Fig7-45 also depicts the same - 2x RX accelerators per slice:

Additionally, table 7-35 lists broadside IDs (0x62, 0x63) for xfr2vbus TX accelerators:

Please clarify the following:

How many Rx instances are available in each instance?
Are there any Tx instances?

Thanks

2 months ago

+1 PratheeshGangadhar 2 months ago

TI__Guru 50931 points

Dhruva Kashyap said:
Are there any Tx instances?

Dhruva Kashyap said:
How many Rx instances are available in each instance?

AFAIK only 1 instance per slice with 0x60 (RD_ID0). Rest looks to be an error in TRM.

0 Dhruva Kashyap 2 months ago in reply to PratheeshGangadhar

TI__Prodigy 120 points

Hi Pratheesh,

Are there any differences in the functionality of the xfr2vbus RX accelerator between the ICSS of AM261x and ICSS-G of AM243x?

I don't see any differences on the TRMs, but is there something else that's been omitted from the documentation?

0 Nilabh Anand 2 months ago in reply to Dhruva Kashyap

TI__Guru 59660 points

Hi Dhruva,

The functionality is same

0 Dhruva Kashyap 2 months ago in reply to Nilabh Anand

TI__Prodigy 120 points

Hi Nilabh,

I'm referring to the LCD interface example from the open pru repo on GitHub (open-pru/examples/LCD_interface at main · TexasInstruments/open-pru · GitHub).

In the PRU1 .asm file (line 110), I see a comment after the xfr2vbus configuration block indicating a difference in the address bus width:

; configure xfr2vbus dma
    ldi    r18, RD_AUTO_64B         ; size 64 bytes, auto increments
    ldi32  r19, ONCHIP_SRAM         ; same address for AM243 and AM261
    ldi    r20, 0                   ; no 48 bit address
    xout   RD_ID1, &r18, 12         ; write address and command
                                    ; AM243x has 48 bit address, AM261 is 32 bit address

Is this something that could cause a difference in functionality?

0 Manoj Koppolu 2 months ago in reply to Dhruva Kashyap

TI__Intellectual 1790 points

Hi Dhruva,

SOC level address is 48bit in AM243x and 32 bit in AM261x (attached image is of am261x)

R18 & R19 configures SOC level read / write address for xfr2vbus , this can be up-to 64bit

As AM261x has 32 bit SOC level address, we are updating only R18 in the code, that is what mentioned in comment.

Thanks & regards,
Manoj.

Arm-based microcontrollers

Arm-based microcontrollers forum

AM2612: Clarification on XFR2VBUS functionality of PRU-ICSS