AM6442: AM2434: MCU-PLUS-SDK-AM243X: Usage GPMC Nor Flash for Bootup and Code storage

Hello Winson Lim,

GPMC Boot is not supported on the AM64x/AM243x devices.

Therefore, you cannot use the GPMC boot mode. We have not made any performance measurements, but based on measurements from other devices, GPMC devices are generally slower compared to OSPI/EMMC .

The GPMC NOR or GPMC PSRAM interfaces are primarily used for storage purposes in AM64x/AM243x devices .

Regards,

Anil.

Hi Swargam

do you mean the bootrom doesnt load the code in the norflash connected to the gpmc or there is no SBL in the MCU-PLUS-SDK-AM243X?  because if its only SBL issue we plan to study further, but if bootrom will not load even setting the bootpin to gpmc nor then we cannot do anything

regards

Hello Winson Lim,

There is no support of the SBL GPMC NOR in the MUC+SDK .

you are able to implement the SBL GPMC NOR application, but the problem is that the SBL GPMC NOR has not been tested in the AM64x SOC.

Even if SBL/ROM Boot works, if the performance degrades, it's not possible to change the ROM GPMC NOR implementation.

Therefore, we recommended to the customer not to go with the GPMC NOR boot mode.

Regards,

Anil.

what is the expected Mbps?  its possible that for our application the speed could be tolerated.  are you able to give an indication?

Hello Winson Lim,

Can you please share what throughput you are expecting with GPMC NOR and OSPI PSRAM?

Right now, I am collecting all the details from other teams, and once I receive them, I should share them with you

Regards,

Anil.

Hi Anil

Thanks so much i appreciate you looking into this

For GPMC NOR : we expecting 125Mbps . But let say (only if) your bootrom cannot achieve this, 

i think we can boot a small SBL, then in SBL we can change some gpmc parameter then we can boost the speed 

so the bigger image can be loaded faster. 

For Ospi Psram: this is the first time we will use ospi for psram. (we intent to XiP from PSRAM)

  in our previous project we worked with SRAM connected to parallel interface, an example device like 

 www.issi.com/.../61-64WV102416FALL-BLL.pdf supports 10ns access time.  maximum 70ns

Hello Winson Lim,

I have discussed this proposal internally with our team, and we have alignment on this approach.

As you mentioned above, once the small size of SBL is loaded and the RBL (ROM Boot Loader) completes, GPMC will reconfigure to 133 MHz and apply optimized timing parameters in the SBL. This should achieve better performance numbers.

Currently, we have not tested NOR on the EVM and don't have throughput numbers. I hope you have received the GPMC NOR daughter card. We can help you enable GPMC NOR on the EVM to test it at your side and obtain test results. Based on these performance numbers, you can decide whether to proceed or not.

If any boot timing requirement is not met, the situation would be that there is no way to change the ROM boot optimizations because they are fixed in the SoC. We would have to accept the ROM boot performance numbers.

If this is acceptable, we are okay with the above proposal. 

Regards,

Anil.

Hi Anil,

Can we provide some code examples for GPMC NOR flash?

The one in MCU+SDK is for NAND.

Regards,

Kien

Hello Kein,

My teammate has already shared the OSPI PSRAM example code.
Please ask the customer to run these examples. I will also share the GPMC NOR example. Currently, I am facing some challenges with the example implementation. Once I resolve them, I will update the status

Regards,

Anil.

Hi Anil

with recommendation in the GPMC daughter card "For non-multiplexed address data 16bit device mode, A [21-1] address lines of AM243x microcontroller will be connected to
A [20-0] of external NOR FLASH memory."  with the 21 addr lines (2^21*16bit) only 32Mb (4MB) can be used?
can the GPMC0_A22 alternative function of GPMC_WPn pad be used to expand up to 8MB?

what are the alternative ways to utilize up to 256Mb for example based on the part in the daughter ?  Looking for recommendation of connections between the daughter card and AM24x.

Thanks

Hello SSR,

Please refer to the image below.

It uses 22-bit address lines and 16-bit data lines. Then you can interface 2^22 × 16-bit, which would be 8MB.

FYI, on the daughter card there is a pin NOR BYTE —the byte or word control pin—with pull-up and pull-down connected by default.

During your testing, you need to pull up for word size and pull down for byte. You can refer to the schematic of the debugger card for more details.

Regards,

Anil.

here is the sbl null that we are using plese rename txt by removing extentionsbl_null.release.hs_fs.tiimage.txt.  

Hello Winson,

Can you please share the GPMC NOR example as well?

We have verified the GPMC Byte pin resistor and boot pin configurations, and they all appear to be correct.

To further analyze the issue, we need the GPMC example to test on our end.

Regards,

Anil.

zip.txt