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AM263P4: Cache Coherence and Data Alignment Issues for AM263P4

mingzhe dai
Prodigy 130 points

Part Number: AM263P4

Based on the analysis of the `tifs_am263px_11_00_00_01` example, when the main core and the HSM core request TRNG services, cache coherence management must be performed before data is sent to the HSM core and after data is received back to the main core, as illustrated below. The `GET_CACHE_ALIGNED_SIZE` macro aligns the size of the data to be cache-managed to a multiple of 128 bytes (the cache line size for buffer alignment).

**Question 1:**  
Is it necessary to enforce alignment when defining the data, e.g`HsmClient_t client __attribute__((aligned(Mcal_CacheP_CACHELINE_ALIGNMENT)))`? Or is it sufficient to perform alignment solely in `CacheP_wbInv`, `CacheP_wb`, and `CacheP_Inv`? As I understand, TI's flow only does the latter. What impact does omitting the former have?

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**Question 2:**  
Are the above data alignment (e.g.HsmClient_t client __attribute__((aligned(Mcal_CacheP_CACHELINE_ALIGNMENT)))) and cache coherence management only necessary when the data is used by multiple cores (R5SS0_CORE0, R5SS0_CORE1, R5SS1_CORE0, R5SS1_CORE1, HSM) and the data resides in a cacheable memory region?  
If the data is used only within R5SS0_CORE0 or is placed in a non-cacheable region, are the above operations unnecessary?

  • 0
    TI__Guru* 88181 points

    Hi,

    mingzhe dai said:
    **Question 1:**  
    Is it necessary to enforce alignment when defining the data, e.g`HsmClient_t client __attribute__((aligned(Mcal_CacheP_CACHELINE_ALIGNMENT)))`? Or is it sufficient to perform alignment solely in `CacheP_wbInv`, `CacheP_wb`, and `CacheP_Inv`? As I understand, TI's flow only does the latter. What impact does omitting the former have?

    There is no restriction in needing the variable to be cache aligned. The requirement is that whenever there is a access from multicore to a cached region, the cache maintainance operations such as CacheP_wbInv, CacheP_wb and CacheP_Inv is needed to be done and this should be done on a cache aligned memory.

    mingzhe dai said:
    Are the above data alignment (e.g.HsmClient_t client __attribute__((aligned(Mcal_CacheP_CACHELINE_ALIGNMENT)))) and cache coherence management only necessary when the data is used by multiple cores (R5SS0_CORE0, R5SS0_CORE1, R5SS1_CORE0, R5SS1_CORE1, HSM) and the data resides in a cacheable memory region?  
    If the data is used only within R5SS0_CORE0 or is placed in a non-cacheable region, are the above operations unnecessary?

    If the core itself is accessing the data and there is no other core modifying the same, then the cache maintenance operation is not required. It is also not required if the region is non-cached.

    Thanks and Regards,

    Nikhil Dasan 

  • 0 in reply to Nikhil Dasan
    Prodigy 130 points

    Question 1:
    Do you mean that I don't need to perform alignment at definition time (e.g., HsmClient_t client __attribute__((aligned(Mcal_CacheP_CACHELINE_ALIGNMENT)))), but only need to pass the size aligned via GET_CACHE_ALIGNED_SIZE as the second argument when calling CacheP_wbInv, CacheP_wb, and CacheP_Inv?

    Question 2:
    Why is Mcal_CacheP_CACHELINE_ALIGNMENT set to 128B in the MCAL project? Is it to maintain uniformity across different platforms? Because I see that the cache line of R5F is 32B.

    Question 3:
    #define GET_CACHE_ALIGNED_SIZE(x) Using the above macro, the computed size is the smallest multiple of 128B that is greater than or equal to x. For example, if x is 128B, the actual aligned region becomes 256B. Is this to prevent affecting other data at the boundary?