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LAUNCHXL2-570LC43: VCLK issues

Danilo A.
Mastermind 33640 points

Part Number: LAUNCHXL2-570LC43
Other Parts Discussed in Thread: HALCOGEN, TMS570LC4357

Hi Team,

Posting on behalf of our customer.

I'll share this E2E post with our customer so he can reply when needed.

I am tryingto get ethernet workoing on the board and part of that is configuring ECLK to output a 50MHz signal (am using RMII mode). To get 50MHz I have to change the VCLK1 divider to 2, halcogen shows an output frequency of 50MHz. 

This clock is also used by the SCIs, all of these SCIs work fine before i change the VCLK divider, after I change it the UART baudrate as measured with a logic analyzer doesnt make sense. Instead of 115200, im measuring 173670. What is interesting is that this baud would make sense if a  clock of 75MHz had been divided with the values halcogen calculates for a 50MHz clock to hit 115200.

This makes me think that VCLK1 is not actually getting changed to the frequency i am setting in halcogen, that said I have had difficulty confirming as my attempts to measure the frequency have not suceeded.

I have found no help in the forums, so any thoughts would be appreciated.

Here is the GCM tab

Here is the SCI config showing the prescaler value

Here is the logic analyzer capture

Regards,

Danilo

  • 0
    Prodigy 50 points

    This is my question, here is the GCM window

    Curiously, if I change the HCLK divider to 0 then the VCLK dividers to hit their original frequencies I don't seem to have this issue and UART works again...

  • 0 in reply to Ian Burgess
    TI__Guru* 77426 points

    Hi Ian,

    There is no issue with SCI driver wise, SCI baudrate settings are configuring correctly only.

    I think the issue lies on clock settings only because i also did route VCLK1 to ECLK and verified frequency and found your setting generating 75Mhz only not 50MHz.

    And i verified divider register as well and it is correctly configured, which is 2 for 50Mhz from 150Mhz of HCLK.

    Then i found we are not meeting below criteria with your configuration, because VLCK(VCLK1) and VCLK2 are not integer multiples.

    And i modified settings as below to meet above criteria:

    However, this is also not helping here and still i can only see 75Mhz. I tested on RM57x board as i don't have TMS570LC4357, could you try with above settings once at your end let me know.

    --
    Thanks & regards,
    Jagadish.

  • 0 in reply to jagadish gundavarapu
    Prodigy 50 points

    Apologies for the late reply, Here is what I'm seeing on the ECLK output with those settings.

    Here is a scope capture of the ECLK output with those settings

    Additionally, UART is nonsense

    Then back with these settings:

    ECLK capture again...

    My scope can only run at 100MHz, but the capture confirms its very close if not exactly 50MHz.

    And finally, UART works

  • 0 in reply to Ian Burgess
    TI__Guru* 77426 points

    Hi Ian,

    Apologies for the delayed response

    Ian Burgess said:

    My scope can only run at 100MHz, but the capture confirms its very close if not exactly 50MHz.

    And finally, UART works

    Good to hear that!

    Do you need any further help on this or we are good?

    --
    Thanks & regards,
    Jagadish.