Part Number: LAUNCHXL2-570LC43
Other Parts Discussed in Thread: HALCOGEN
Hi Team,
Posting on behalf of our customer.
I'll share this E2E post with our customer so he can reply when needed.
I am tryingto get ethernet workoing on the board and part of that is configuring ECLK to output a 50MHz signal (am using RMII mode). To get 50MHz I have to change the VCLK1 divider to 2, halcogen shows an output frequency of 50MHz.
This clock is also used by the SCIs, all of these SCIs work fine before i change the VCLK divider, after I change it the UART baudrate as measured with a logic analyzer doesnt make sense. Instead of 115200, im measuring 173670. What is interesting is that this baud would make sense if a clock of 75MHz had been divided with the values halcogen calculates for a 50MHz clock to hit 115200.
This makes me think that VCLK1 is not actually getting changed to the frequency i am setting in halcogen, that said I have had difficulty confirming as my attempts to measure the frequency have not suceeded.
I have found no help in the forums, so any thoughts would be appreciated.
Here is the GCM tab
Here is the SCI config showing the prescaler value
Here is the logic analyzer capture
Regards,
Danilo
