AM263P4: SDFM peripheral sync to PWM (SDSYNC) not working

Hello Micah,

The SDSYNC event requires three things to be properly configured — if any are missing, toggling the SysConfig checkbox will appear to have no effect:

1. Verify `SDDFPARM.SDSYNCEN` is actually set in hardware

In SysConfig, ensure "Use PWM Synchronization" is enabled in the DataFilter Settings section, and that the SDSYNC source is explicitly set (e.g., "SDFM sync source is PWM0 SOCA") [1]. But don't trust SysConfig alone — read back the `SDDFPARMx` register and confirm bit 12 (SDSYNCEN) = 1. If this bit isn't set, the SDSYNC signal is gated off at the first AND gate before it reaches the Data Filter Unit.

2. Verify `SDSYNCx.SYNCSEL` is correctly mapped

The `SYNCSEL[5:0]` bits select which PWM SOCA/SOCB signal provides the sync pulse. For PWM0 SOCA, `SYNCSEL` should be 0. Confirm this in the generated code or via register read.

3. Verify PWM0 is actually generating the SOCA event

The SDSYNC mechanism relies on the PWM module producing a SOCA pulse. If PWM0 isn't configured to generate SOCA events, the SDFM will never receive a sync trigger. Also ensure your PWM is in up-count or down-count mode — if using up-down count mode, you must guarantee only one SDSYNC event per PWM period, otherwise the filter synchronizer corrupts SDFM timing by providing two pulses per cycle.

4. Confirm operation by checking data-ready timing

The definitive way to verify SDSYNC is working: check that filter data-ready interrupts align with your PWM SOCA period rather than occurring at arbitrary SDFM clock intervals. If data-ready events are PWM-aligned, synchronization is active.

5. Clear stale interrupt flags

A related issue seen on AM263P4: if you're using data-ready interrupts, ensure you clear the SDFM interrupt flag immediately after ISR registration. A stale pre-existing flag can prevent new interrupts from firing.

Does SDDATAx Use Synchronized Data?

Yes — SDDATAx provides synchronized data even without the FIFO enabled.

The SDSYNC signal feeds directly into the Data Filter Unit, where it resets the DOSR counter and restarts data capture. The SDDATAx output comes from the "Data Shift" block downstream of the synchronized SINCx filter but upstream of the FIFO. This means the synchronization occurs in the filter pipeline itself, not in the FIFO stage.

The FIFO's Wait-for-Sync (WTSYNCEN) feature is a *separate* mechanism that controls when the FIFO starts populating after an SDSYNC event. That feature is irrelevant when FIFO is disabled. Your direct SDDATAx reads will reflect PWM-synchronized filter output.

Best Regards,

Masoud

Hi,

I can report this to SysConfig team. Sometimes, we see all the functions are not supported in SysConfig.

SDSYNC does not gate the SDFM input stream itself. The SDFM modulator data/clock continues to run continuously, and the data filter continues to produce output based on the selected filter type and OSR. The SDSYNC event is used to synchronize/reset the SDFM data filter timing to the selected sync source, such as an ePWM event. Therefore, enabling SDSYNC may not visibly change the raw data value unless you are observing the filter timing/data-ready phase relative to the PWM event.

Also, the SDDATAx value is the data-filter output, so it is affected by the SDFM data-filter configuration. FIFO is not required for this path. FIFO only changes how filtered samples are buffered/read; it is not required for synchronized SDFM operation.

Best Regards,

Masoud