AM625: AM625:AM625 GPMC Usage

z ryan

Part Number: AM625
Other Parts Discussed in Thread: SYSCONFIG, AM5728

Our GPMC interface requires separate data and address buses (non-multiplexed mode), with an 8-bit data bus and a 23-bit address bus.
My configuration is as follows:

gpmc0_pins_default: gpmc0-pins-default {
bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x003C, PIN_INPUT, 0) /* (K19) GPMC0_AD0 */
AM62X_IOPAD(0x0040, PIN_INPUT, 0) /* (L19) GPMC0_AD1 */
AM62X_IOPAD(0x0044, PIN_INPUT, 0) /* (L20) GPMC0_AD2 */
AM62X_IOPAD(0x0048, PIN_INPUT, 0) /* (L21) GPMC0_AD3 */
AM62X_IOPAD(0x004C, PIN_INPUT, 0) /* (M21) GPMC0_AD4 */
AM62X_IOPAD(0x0050, PIN_INPUT, 0) /* (L17) GPMC0_AD5 */
AM62X_IOPAD(0x0054, PIN_INPUT, 0) /* (L18) GPMC0_AD6 */
AM62X_IOPAD(0x0058, PIN_INPUT, 0) /* (M20) GPMC0_AD7 */

AM62X_IOPAD(0x0090, PIN_OUTPUT, 0) /* (K17) GPMC0_BE0n_CLE */
AM62X_IOPAD(0x0094, PIN_OUTPUT, 0) /* (K18) GPMC0_BE1n */

AM62X_IOPAD(0x00A8, PIN_OUTPUT, 0) /* (J18) GPMC0_CSn0 */
AM62X_IOPAD(0x00AC, PIN_OUTPUT, 0) /* (H17) GPMC0_CSn1 */
AM62X_IOPAD(0x00B0, PIN_OUTPUT, 0) /* (H18) GPMC0_CSn2 */

AM62X_IOPAD(0x0098, PIN_INPUT, 0) /* (P21) GPMC0_WAIT0 */
AM62X_IOPAD(0x0084, PIN_OUTPUT, 0) /* (K20) GPMC0_ADVn_ALE */
AM62X_IOPAD(0x007C, PIN_OUTPUT, 0) /* (M19) GPMC0_CLK */
AM62X_IOPAD(0x00A4, PIN_OUTPUT, 0) /* (J19) GPMC0_DIR */
AM62X_IOPAD(0x0088, PIN_OUTPUT, 0) /* (K21) GPMC0_OEn_REn */
AM62X_IOPAD(0x008c, PIN_OUTPUT, 0) /* (J17) GPMC0_WEn */

AM62X_IOPAD(0x00B8, PIN_OUTPUT, 1) /* (R21) VOUT0_DATA0 to GPMC0_A0 */
AM62X_IOPAD(0x00BC, PIN_OUTPUT, 1) /* (P18) VOUT0_DATA1 to GPMC0_A1 */
AM62X_IOPAD(0x00C0, PIN_OUTPUT, 1) /* (R18) VOUT0_DATA2 to GPMC0_A2 */
AM62X_IOPAD(0x00C4, PIN_OUTPUT, 1) /* (R19) VOUT0_DATA3 to GPMC0_A3 */
AM62X_IOPAD(0x00C8, PIN_OUTPUT, 1) /* (R20) VOUT0_DATA4 to GPMC0_A4 */
AM62X_IOPAD(0x00CC, PIN_OUTPUT, 1) /* (T20) VOUT0_DATA5 to GPMC0_A5 */
AM62X_IOPAD(0x00D0, PIN_OUTPUT, 1) /* (T21) VOUT0_DATA6 to GPMC0_A6 */
AM62X_IOPAD(0x00D4, PIN_OUTPUT, 1) /* (T19) VOUT0_DATA7 to GPMC0_A7 */
AM62X_IOPAD(0x00D8, PIN_OUTPUT, 1) /* (U21) VOUT0_DATA8 to GPMC0_A8 */
AM62X_IOPAD(0x00DC, PIN_OUTPUT, 1) /* (R17) VOUT0_DATA9 to GPMC0_A9 */
AM62X_IOPAD(0x00E0, PIN_OUTPUT, 1) /* (T18) VOUT0_DATA10 to GPMC0_A10 */
AM62X_IOPAD(0x00E4, PIN_OUTPUT, 1) /* (U20) VOUT0_DATA11 to GPMC0_A11 */
AM62X_IOPAD(0x00E8, PIN_OUTPUT, 1) /* (U19) VOUT0_DATA12 to GPMC0_A12 */
AM62X_IOPAD(0x00EC, PIN_OUTPUT, 1) /* (V21) VOUT0_DATA13 to GPMC0_A13 */
AM62X_IOPAD(0x00F0, PIN_OUTPUT, 1) /* (U18) VOUT0_DATA14 to GPMC0_A14 */
AM62X_IOPAD(0x00F4, PIN_OUTPUT, 1) /* (V20) VOUT0_DATA15 to GPMC0_A15 */

AM62X_IOPAD(0x00F0, PIN_OUTPUT, 1) /* (W21) VOUT0_HSYNC to GPMC0_A16 */
AM62X_IOPAD(0x00FC, PIN_OUTPUT, 1) /* (T17) VOUT0_DE to GPMC0_A17 */
AM62X_IOPAD(0x0100, PIN_OUTPUT, 1) /* (T16) VOUT0_VSYNC to GPMC0_A18 */
AM62X_IOPAD(0x0104, PIN_OUTPUT, 1) /* (U17) VOUT0_PCLK to GPMC0_A19 */

AM62X_IOPAD(0x00B4, PIN_OUTPUT, 2) /* (H19) GPMC0_CSn3 to GPMC0_A20 */
AM62X_IOPAD(0x009C, PIN_OUTPUT, 2) /* (P17) GPMC0_WAIT1 to GPMC0_A21 */
AM62X_IOPAD(0x00A0, PIN_OUTPUT, 2) /* (J20) GPMC0_WPn to GPMC0_A22 */
>;
};

Questions:
1.Could you help verify if this configuration and hardware design are feasible?
2.Apart from the pin configuration, are there any required modifications to the settings below?

&gpmc0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&gpmc0_default_pins>;
#address-cells = <2>;
#size-cells = <1>;

nand@0,0 {
compatible = "ti,am64-nand";
reg = <0 0 64>; /* device IO registers */
interrupt-parent = <&gpmc0>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
rb-gpios = <&gpmc0 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
ti,nand-xfer-type = "prefetch-polled";
ti,nand-ecc-opt = "bch8"; /* BCH8: Bootrom limitation */
ti,elm-id = <&elm0>;
nand-bus-width = <8>;
gpmc,device-width = <1>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <40>;
gpmc,cs-wr-off-ns = <40>;
gpmc,adv-on-ns = <0>;
gpmc,adv-rd-off-ns = <25>;
gpmc,adv-wr-off-ns = <25>;
gpmc,we-on-ns = <0>;
gpmc,we-off-ns = <20>;
gpmc,oe-on-ns = <3>;
gpmc,oe-off-ns = <30>;
gpmc,access-ns = <30>;
gpmc,rd-cycle-ns = <40>;
gpmc,wr-cycle-ns = <40>;
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wr-access-ns = <40>;
gpmc,wr-data-mux-bus-ns = <0>;

partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;

partition@0 {
bootph-all;
label = "NAND.tiboot3";
reg = <0x00000000 0x00200000>; /* 2M */
};
partition@200000 {
bootph-all;
label = "NAND.tispl";
reg = <0x00200000 0x00200000>; /* 2M */
};
partition@400000 {
bootph-all;
label = "NAND.tiboot3.backup"; /* 2M */
reg = <0x00400000 0x00200000>; /* BootROM looks at 4M */
};
partition@600000 {
bootph-all;
label = "NAND.u-boot";
reg = <0x00600000 0x00400000>; /* 4M */
};
partition@a00000 {
bootph-all;
label = "NAND.u-boot-env";
reg = <0x00a00000 0x00040000>; /* 256K */
};
partition@a40000 {
bootph-all;
label = "NAND.u-boot-env.backup";
reg = <0x00a40000 0x00040000>; /* 256K */
};
partition@a80000 {
bootph-all;
label = "NAND.file-system";
reg = <0x00a80000 0x3f580000>;
};
};
};
};

1 month ago

0 Hong Guan64 1 month ago

TI__Guru* 77050 points

Have we tested the nand device identification, i.e. "nand info" @u-boot prompt?
Best,
-Hong

0 z ryan 29 days ago in reply to Hong Guan64

Prodigy 90 points

We are connecting to an FPGA. We need to confirm whether this pin multiplexing setup is correct, and find out what other modifications are required for communication with the FPGA.

0 Hong Guan64 28 days ago in reply to z ryan

TI__Guru* 77050 points

Will you share the schematics on FPGA connections with GPMC?
Best,
-Hong

0 z ryan 23 days ago in reply to Hong Guan64

Prodigy 90 points

The above content defines the pin multiplexing for GPMC hardware design. What adjustments are required for this GPMC pin configuration?

0 Mark M 22 days ago

TI__Mastermind 30561 points

Hi,

This looks like the "AMC package" of AM625... please confirm.

Are there any issues with the NAND? Or just the FPGA communication?

I identify two mistakes:

z ryan said:
AM62X_IOPAD(0x007C, PIN_OUTPUT, 0) /* (M19) GPMC0_CLK */

GPMC0_CLK must be PIN_INPUT - GPMC uses the output clock to latch receive data, so it must be output and input

z ryan said:
AM62X_IOPAD(0x00F0, PIN_OUTPUT, 1) /* (W21) VOUT0_HSYNC to GPMC0_A16 */

The address offset 0x00F0 is incorrect - should instead be 0x00F8. 0x00F0 is already used with (U18) VOUT0_DATA14 to GPMC0_A14

I recommend using Sysconfig (https://dev.ti.com/sysconfig) with below setting for Use Case:

Regards,
Mark

0 z ryan 15 days ago in reply to Mark M

Prodigy 90 points

We need the GPMC clock to keep outputting continuously; what is the appropriate modification?

0 Mark M 15 days ago in reply to z ryan

TI__Mastermind 30561 points

Hi,

The GPMC0_CLK has the continuously outputting mux mode option GPMC0_FCLK_MUX on Mux Mode 3 of the same pin.

Change the device tree...
FROM:
AM62X_IOPAD(0x007c, PIN_INPUT|PIN_DRIVE_STRENGTH_NOMINAL, 0) /* (P25) GPMC0_CLK */ (from SYSCONFIG)
AM62X_IOPAD(0x007C, PIN_OUTPUT, 0) /* (M19) GPMC0_CLK */ (from your post)

TO:
AM62X_IOPAD(0x007c, PIN_INPUT|PIN_DRIVE_STRENGTH_NOMINAL, 3) /* (P25) GPMC0_CLK */ (from SYSCONFIG)
AM62X_IOPAD(0x007C, PIN_OUTPUT, 3) /* (M19) GPMC0_CLK */ (from your post)

This free-running clock is the input to GPMC selected through GPMC_CLKSEL_CLK_SEL in MAIN_CTRL_MMR_CFG0_GPMC_CLKSEL Register
1'b0 - MAIN_PLL0_HSDIV3_CLKOUT (133/100/80 MHz)
1'b1 - MAIN_PLL2_HSDIV7_CLKOUT (100/66 MHz)

See https://www.ti.com/lit/pdf/SPRUIV7

GPMCFCLKDIVIDER in GPMC_CONFIG1_j Register does not have any effect on the clock frequency of the free-running clock - the free-running clock cannot be divided down.

Hope this helps,
Mark

0 z ryan 15 days ago in reply to Mark M

Prodigy 90 points

The default clock of MAIN_PLL0_HSDIV3_CLKOUT is 133MHz. How can I configure the frequency of GPMC0_FCLK_MUX? For example, clocks = <&k3_clks 80 2> is 100MHz. How can I set MAIN_PLL0_HSDIV3_CLKOUT to 50MHz or 100MHz?

0 z ryan 14 days ago in reply to Mark M

Prodigy 90 points

Currently, GPMC_CLK is configured as GPMC0_FCLK_MUX and can continuously output.
However, we need to control this clock frequency. By default, without modifying 0x00108180, it outputs 133MHz, but we need to output 50MHz. How can I modify this clock frequency through the device tree?
If I modify MAIN_PLL0_HSDIV3_CLKOUT or MAIN_PLL2_HSDIV7_CLKOUT, would the impact be significant?

0 Mark M 14 days ago in reply to z ryan

TI__Mastermind 30561 points

Hi,

For 50MHz, you would need to...

1) set GPMC_CLKSEL_CLK_SEL to 1'b1 - MAIN_PLL2_HSDIV7_CLKOUT

2) and also change the change the HSDIV7 to 20. There are no other peripherals clocked by MAIN_PLL2_HSDIV7_CLKOUT so you would not affect anything except for GPMC. With the slower FCLK clock going into the GPMC logic, all GPMC timings will also be slowed down.

MAIN_PLL2_HSDIV7_CLKOUT:
1000/10 = (FOUTPOSTDIV/10) = 100MHz
1000/15 = (FOUTPOSTDIV/15) = 66MHz
1000/20 = (FOUTPOSTDIV/20) = 50MHz

Let me ask a colleague if it is possible to make this modification or if there are forced restrictions. There is a warning in the TRM:
WARNING: PLL register descriptions are provided for debug purposes only. These registers should not be manipulated directly from software. PLL programming and configuration should only be performed using the appropriate APIs provided by TISCI services in TI's Processor Software Development Kits (SDKs). TISCI: Power Management (PM)

Refer to 6.4.5 PLLs in the TRM

And the SysConfig Clock Tree Tool has this selection grey and fixed to 100MHz...

Regards,
Mark

0 Mark M 14 days ago in reply to Mark M

TI__Mastermind 30561 points

Actually, further down in the SysConfig Clock Tree Tool (https://dev.ti.com/sysconfig) is the GPMC0 section and it allows you to modify the HSDIV to 50MHz.

Resulting .syscfg output is below:

/**
 * These arguments were used when this file was generated. They will be automatically applied on subsequent loads
 * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
 * @cliArgs --device "AM62x" --part "AM6251-G" --package "ALW" --product "CLOCKTREE-AM6X@1.1.4"
 * @v2CliArgs --device "AM625" --package "FCBGA (ALW)" --variant "AM6251-G" --product "CLOCKTREE-AM6X@1.1.4"
 * @versions {"tool":"1.27.1+4634"}
 */

/**
 * Write custom configuration values to the imported modules.
 */
const hsdiv13 = system.clockTree["postdiv4_16ff2"];
hsdiv13.divideValue7 = 20;

I should mention for GPMC synchronous burst writes while using div-by-1 or div-by-2 clock, WAIT pin and WAITMONITORINGTIME parameter needs attention to support burst writes. Refer to TRM 12.4.3.4.7.3.1.4 Wait Monitoring During Synchronous Write Access

WAIT monitoring is supported for all configurations except GPMC_CONFIG1_i[19-18]
WAITMONITORINGTIME = 0x0 (where i = 0 to 3) for write bursts with a clock divider of 1 or 2
(the GPMC_CONFIG1_i[1-0] GPMCFCLKDIVIDER bit field is equal to 0x0 or 0x1, respectively).

This E2E also: AM5728: Wait monitoring time AM5728: Wait monitoring time

Regards,
Mark

0 Hong Guan64 14 days ago in reply to Mark M

TI__Guru* 77050 points

Adding to Mark's comment, here is how to re-configure GPMC_FCLK to 50Mhz via "k3conf" or "dts/dtso" file
- I'm attaching a log showing how to do it via "k3conf" @kernel

k3conf set parent_clock 80 0 2
k3conf set clock 80 2 50000000

- The re-configuration on GPMC_FLCK in *dts/*dtso

assigned-clocks = <&k3_clks 80 0>;
assigned-clock-parents = <&k3_clks 80 2>;
assigned-clock-rates = <50000000>;

Best,
-Hong

Fullscreen 4606.am62-lp_gpmc_clk_50M.log Download

root@am62xx-lp-evm:~# uname -a
Linux am62xx-lp-evm 6.6.32-ti-g6de6e418c80e-dirty #1 SMP PREEMPT Fri Jul 26 14:32:20 UTC 2024 aarch64 GNU/Linux
root@am62xx-lp-evm:~# k3conf dump clock 80
|------------------------------------------------------------------------------|
| VERSION INFO                                                                 |
|------------------------------------------------------------------------------|
| K3CONF | (version 0.3-nogit built Thu Jul 25 14:13:02 UTC 2024)              |
| SoC    | AM62X SR1.0                                                         |
| SYSFW  | ABI: 4.0 (firmware version 0x000a '10.0.8--v10.00.08 (Fiery Fox))') |
|------------------------------------------------------------------------------|

|-------------------------------------------------------------------------------------------------------------------------|
| Device ID | Clock ID | Clock Name                                                   | Status          | Clock Frequency |
|-------------------------------------------------------------------------------------------------------------------------|
|    80     |     0    | DEV_GPMC0_FUNC_CLK                                           | CLK_STATE_READY | 133333333       |
|    80     |     1    | DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK  | CLK_STATE_READY | 133333333       |
|    80     |     2    | DEV_GPMC0_FUNC_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT7_CLK | CLK_STATE_READY | 100000000       |
|    80     |     3    | DEV_GPMC0_PI_GPMC_RET_CLK                                    | CLK_STATE_READY | 0               |
|    80     |     4    | DEV_GPMC0_PO_GPMC_DEV_CLK                                    | CLK_STATE_READY | 0               |
|    80     |     5    | DEV_GPMC0_VBUSM_CLK                                          | CLK_STATE_READY | 250000000       |
|-------------------------------------------------------------------------------------------------------------------------|

root@am62xx-lp-evm:~# k3conf set parent_clock 80 0 2
|------------------------------------------------------------------------------|
| VERSION INFO                                                                 |
|------------------------------------------------------------------------------|
| K3CONF | (version 0.3-nogit built Thu Jul 25 14:13:02 UTC 2024)              |
| SoC    | AM62X SR1.0                                                         |
| SYSFW  | ABI: 4.0 (firmware version 0x000a '10.0.8--v10.00.08 (Fiery Fox))') |
|------------------------------------------------------------------------------|

|-------------------------------------------------------------------------------|
| Clock information                                                             |
|-------------------------------------------------------------------------------|
| Device ID | Clock ID | Clock Name         | Status          | Clock Frequency |
|-------------------------------------------------------------------------------|
|    80     |     0    | DEV_GPMC0_FUNC_CLK | CLK_STATE_READY | 100000000       |
|-------------------------------------------------------------------------------|

|------------------------------------------------------------------------------------------------------------------------|
| Clock Parent information                                                                                               |
|------------------------------------------------------------------------------------------------------------------------|
| Selected | Clock ID | Clock Name                                                   | Status          | Clock Frequency |
|------------------------------------------------------------------------------------------------------------------------|
|          |     1    | DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK  | CLK_STATE_READY | 133333333       |
|   ==>    |     2    | DEV_GPMC0_FUNC_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT7_CLK | CLK_STATE_READY | 100000000       |
|------------------------------------------------------------------------------------------------------------------------|

root@am62xx-lp-evm:~# k3conf set clock 80 2 50000000
|------------------------------------------------------------------------------|
| VERSION INFO                                                                 |
|------------------------------------------------------------------------------|
| K3CONF | (version 0.3-nogit built Thu Jul 25 14:13:02 UTC 2024)              |
| SoC    | AM62X SR1.0                                                         |
| SYSFW  | ABI: 4.0 (firmware version 0x000a '10.0.8--v10.00.08 (Fiery Fox))') |
|------------------------------------------------------------------------------|

|-------------------------------------------------------------------------------------------------------------------------|
| Device ID | Clock ID | Clock Name                                                   | Status          | Clock Frequency |
|-------------------------------------------------------------------------------------------------------------------------|
|    80     |     0    | DEV_GPMC0_FUNC_CLK                                           | CLK_STATE_READY | 50000000        |
|    80     |     1    | DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK  | CLK_STATE_READY | 133333333       |
|    80     |     2    | DEV_GPMC0_FUNC_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT7_CLK | CLK_STATE_READY | 50000000        |
|    80     |     3    | DEV_GPMC0_PI_GPMC_RET_CLK                                    | CLK_STATE_READY | 0               |
|    80     |     4    | DEV_GPMC0_PO_GPMC_DEV_CLK                                    | CLK_STATE_READY | 0               |
|    80     |     5    | DEV_GPMC0_VBUSM_CLK                                          | CLK_STATE_READY | 250000000       |
|-------------------------------------------------------------------------------------------------------------------------|

root@am62xx-lp-evm:~# k3conf dump clock 80
|------------------------------------------------------------------------------|
| VERSION INFO                                                                 |
|------------------------------------------------------------------------------|
| K3CONF | (version 0.3-nogit built Thu Jul 25 14:13:02 UTC 2024)              |
| SoC    | AM62X SR1.0                                                         |
| SYSFW  | ABI: 4.0 (firmware version 0x000a '10.0.8--v10.00.08 (Fiery Fox))') |
|------------------------------------------------------------------------------|

|-------------------------------------------------------------------------------------------------------------------------|
| Device ID | Clock ID | Clock Name                                                   | Status          | Clock Frequency |
|-------------------------------------------------------------------------------------------------------------------------|
|    80     |     0    | DEV_GPMC0_FUNC_CLK                                           | CLK_STATE_READY | 50000000        |
|    80     |     1    | DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK  | CLK_STATE_READY | 133333333       |
|    80     |     2    | DEV_GPMC0_FUNC_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT7_CLK | CLK_STATE_READY | 50000000        |
|    80     |     3    | DEV_GPMC0_PI_GPMC_RET_CLK                                    | CLK_STATE_READY | 0               |
|    80     |     4    | DEV_GPMC0_PO_GPMC_DEV_CLK                                    | CLK_STATE_READY | 0               |
|    80     |     5    | DEV_GPMC0_VBUSM_CLK                                          | CLK_STATE_READY | 250000000       |
|-------------------------------------------------------------------------------------------------------------------------|

root@am62xx-lp-evm:~#

Arm-based microcontrollers

Arm-based microcontrollers forum

AM625: AM625:AM625 GPMC Usage