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MSPM0G3507: When does SPI1 CTL1.POD bit take effect?

Alan
Prodigy 205 points

Part Number: MSPM0G3507

I have a case where I would like to use my device with the SPI set to peripheral mode, and I would like to be able to tri-state the POCI line mid-transaction (i.e. while the nCS line is asserted).  CTL1.POD seems ideally placed to do this, based on the description in the reference manual.  With a pull-up attached to that line, I would expect to see the effect of setting the bit as the line is pulled high.  This does not seem to be happening, though - the line keeps driving data out as the controller keeps clocking further words.

If I set the bit mid-way through the controller sending a series of words to my MSPM0-based peripheral, when should I expect to see the POCI stop driving data out? Do I need to perform any other actions, or is setting the bit sufficient?  I can't find an example that uses this bit - is there an app note?

  • 0
    Guru 102595 points

    Some/most of the CTL0/1 bits require a disable/enable (CTL1:ENABLE=0 then =1) to take effect, though I haven't tried this one in particular.

    If there's no ongoing transaction, this disable/enable is benign. I'm not sure what would happen mid-transaction.

    [Edit: You might get some mileage out of switching the IOMUX to PF=0. The SPI unit wouldn't notice.]

  • 0 in reply to Bruce McKenney
    Prodigy 205 points

    Thanks for the suggestion, I'll give that a try.  If POD requires a disable/enable cycle, then it does make me wonder what the point of it is when setting PF=0 would be somewhat simpler.

  • 0 in reply to Alan
    Prodigy 205 points

    Update: setting IOMUX PF=0 has pretty-much the effect that I wanted, but I'm still interested to know what CTL1.POD does (or is supposed to do!) in case there's some subtlety that I'm yet to uncover.

  • 0 in reply to Alan
    Guru 102595 points

    I don't know what the Use Case for this is, even given the bit description in the TRM. More so considering your experiments indicating that it requires an Enable-toggle.

    I did once construct a broadcast-SPI bus, but I used the equivalent of PF=0 and it was fine.

  • 0 in reply to Bruce McKenney
    TI__Mastermind 30435 points

    Hey Alan,

    My understanding is that peripheral should be disabled when changing anything in CTL0/CTL1, so yes, I think the peripheral needs to be disabled to set this bit.  I'm also not sure what the use case was for when our systems and architecture team defined this feature.  I guess it allows us to sill monitor the PICO line with the ability to re-configure in-between bytes to drive the POCI bus. 

    I was also going to recommend just using IOMUX.  You can use the PF bits as mentioned.  It doesn't exactly help you here, but you can also set the pin to be Hi-Z in the IOMUX so multiple devices could drive the bus without issue, but it could still pull the bus low and you could still have data collisions. 

    Thanks,

    JD