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MSPM0G3519: I2C module's bus busy bit set/clear conditions

Wayne Huang
Genius 17125 points

Part Number: MSPM0G3519
Other Parts Discussed in Thread: MSPM0G3507

Hi champs,

 

I am asking this for our customers.

In the I2C modules for MSPM0G3507 and G3519,

Would you please confirm these bus busy bits set/clear condisitons?

CSR Register[6] BUSBSY

CSR Register[0] BUSBSY

TSR Register[6] BUSBSY

  • 0
    TI__Genius 17125 points

    Hi champs,

    Do you have any update?

  • 0
    Guru 102725 points

    [No one else seems to be answering, so here are my observations:]

    The CSR BUSBSY/BUSY bits are described in TRM (SLAU846D) Sec 25.2.3.2 and Tables 25-12 and 25-56. There's also Erratum I2C_ERR_13 [Ref Errata (SLAZ758D) p. 12].

    In my experiments (last year) I was unable to reliably use them based on their observed behavior, so I don't. Rather I use the TXDONE/RXDONE events along with the ERR bit, and (only) after that a check for IDLE.

    The TSR BUSBSY is described in TRM Table 25-69, which is rather sparse. That said, I haven't thought of a way to use it (since the Target side has no influence), rather relying on the START and FIFO events.

  • 0 in reply to Bruce McKenney
    TI__Genius 17125 points

    Hi Bruce,

    Thank you very much for your information.

    Yes, the user thinks the doc is not clear, either, so I am asking TI internal to clarify it so that we can know how to use it correctly.

  • 0 in reply to Wayne Huang
    TI__Mastermind 30406 points

    Hi Wayne,

    Let me jump here give some comments:

    Controller Mode:

    There will have two flag bits: CSR.BUSBSY(I2C Bus is Busy) and CSR.BUSY(I2C Controller FSM Busy)

    • CSR.BUSBSY: This used to detect if I2C bus finish transfer, so the clear even will be Stop signal or timeout signal, set event will be Start signal.

    • CSR.BUSY: This is Controller FSM busy bit, if Controller need have some action to I2C bus, this bit will be set within 3 functional clock. Then cleared after addressing this action. Check Errata -> ADC_ERR_13. If user want polling this bit to see if finish I2C data transmission, need add some delay before checking.

    Target Mode:

    TSR.BUSBSY keep same logical with CSR.BUSBSY. TSR no other FSM busy bit.

    Thanks!

    Best Regards

    Johnson