• State
  • Replies 5 replies
  • Subscribers 32 subscribers
  • Views 73 views
  • Users 0 members are here
Support feedback
Options
Options
Related

AM2612: Maximum OSPI0 clock output keeps 7.5MHz

Robert Huang
Prodigy 61 points

Part Number: AM2612
Other Parts Discussed in Thread: TIDA-010979, SYSCONFIG

Hi Experts,

We used same design including AM2612 and flash (ISSI IS25LP016) in TIDA-010979,  which interface is OSPI0 .

Currently we can successfully access the flash at low clock frequency(about 2MHz). Next we would like to higher it. In SYSCONFIG file, for OSPI configuration, whenever the input clock frequency(Hz) is 240000000 (240MHz), and input clock divider is either 8 or 4, the clock measured is always 7.5MHz (expect it's supposed to be 30MHz or 60MHz). Even we tried to use OSPI_setBaudRateDiv(ospiHandle, 8 or 4 or 2) API to enforce setting again after Board_flashOpen() and it keeps the same.

Could you please kindly help check and provide your suggestion? Thanks.

BR, Robert Huang 

  • 0
    TI__Expert 6465 points

    Hi Robert,

    Can you please tell me which SDK (MCU PLUS SDK version) are you using? 

    Thanks,

    Aswin

  • 0 in reply to Aswin Sankar
    Prodigy 61 points

    Hi Aswin,

    It's mcu_plus_sdk_am261x_11_01_00_19 folder name.

    BR, Robert Huang

  • 0 in reply to Robert Huang
    TI__Expert 6465 points

    Hi Robert, 

    Can you please share me how the clock configuration clock configuration.

    A screen shot of the OSPI Sysconfig configuration and the OSPI Clock configuration from clock tree would be enough. I wanted to see what are the 

    PLL dividers, GM CLK dividers, and the baud rate divider.

    Thanks & Regards,

    Aswin 

  • 0 in reply to Aswin Sankar
    Prodigy 61 points

    Hi Aswin,

    Please see attached snapshot. Don't know what dimension means while Insert -> Image/Video/File and I key in the original snapshot size for each. Hopefully you can check them out clearly. Thanks.

    BR, Robert Huang

  • 0 in reply to Robert Huang
    TI__Expert 6465 points

    Hi Robert, 

    Please try this configuration.

    PLL configs are done from SBL. So in your SBL, here I have taken this project as sbl: examples\drivers\boot\sbl_ospi_multicore_elf\am261x-som

    1. Configuration in Clock tree tool

    2. Configuration in OSPI Section. Turn OFF PHY

    Do the same process in application as well. Both the clock tree and OSPI PHY configuration

    In application, the PLL configuration is necessary because based on its inputs, the application also verifies if the PLL configuration made in SBL matches with what that is configured.

    I am attaching my sysconfigs

    1. SBL Sysconfig: examples\drivers\boot\sbl_ospi_multicore_elf\am261x-som

    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/908/8270.example.syscfg

    2. Application Sysconfig: examples\hello_world\am261x-som\r5fss0-0_freertos

    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/908/8270.example.syscfg

    This is the output obtained. Boot media clock is 30MHz which is OSPI clock.

    Thanks & Regards,

    Aswin