AM2612: Maximum OSPI0 clock output keeps 7.5MHz

Hi Robert,

Can you please tell me which SDK (MCU PLUS SDK version) are you using? 

Thanks,

Aswin

Hi Aswin,

It's mcu_plus_sdk_am261x_11_01_00_19 folder name.

BR, Robert Huang

Hi Robert, 

Can you please share me how the clock configuration clock configuration.

A screen shot of the OSPI Sysconfig configuration and the OSPI Clock configuration from clock tree would be enough. I wanted to see what are the 

PLL dividers, GM CLK dividers, and the baud rate divider.

Thanks & Regards,

Aswin 

Hi Aswin,

Please see attached snapshot. Don't know what dimension means while Insert -> Image/Video/File and I key in the original snapshot size for each. Hopefully you can check them out clearly. Thanks.

BR, Robert Huang

Hi Robert, 

Please try this configuration.

PLL configs are done from SBL. So in your SBL, here I have taken this project as sbl: examples\drivers\boot\sbl_ospi_multicore_elf\am261x-som

1. Configuration in Clock tree tool

2. Configuration in OSPI Section. Turn OFF PHY

Do the same process in application as well. Both the clock tree and OSPI PHY configuration

In application, the PLL configuration is necessary because based on its inputs, the application also verifies if the PLL configuration made in SBL matches with what that is configured.

I am attaching my sysconfigs

1. SBL Sysconfig: examples\drivers\boot\sbl_ospi_multicore_elf\am261x-som

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/908/8270.example.syscfg

2. Application Sysconfig: examples\hello_world\am261x-som\r5fss0-0_freertos

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/908/8270.example.syscfg

This is the output obtained. Boot media clock is 30MHz which is OSPI clock.

Thanks & Regards,

Aswin

Hi Aswin,

I used sbl_ospi_multicore_elf_am261x-lp_r5fss0-0_nortos_ti-arm-clang project as my custom board project and made some changes as your mention as below git snapshot (before versus after). The boot media clock changed to 30MHz as yours but the waveform measured at opsi clock pin still keeps about 7.5MHz square waveform. Could you please kindly help check any possibilities? Thanks.

Hi Robert, 

Can you please provide me the value of these registers.

Thanks & Regards,

Aswin

Hi Robert, 

To clarify if these registers are configured correctly then the OSPI output freq should be 30Hz. So we can check these registers to ensure if they are configured correctly.

Hi Aswin, 

We flashed 30MHz setting configuration + Disable PHY mode on both SBL and application and running output message as below for your reference.

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/908/sbl_5F00_ospi_5F00_multicore_5F00_elf.debug.tiimagehttps://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/908/hello_5F00_world.debug.mcelf

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/908/sbl_5F00_example.syscfg https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/908/hw_5F00_example.syscfg

Hi Robert,

The register dump values seem to differ between my setup and your setup.

My Reg Values
TOP_RCM_PLL_CORE_M2NDIV [0x53200410] = 0x00010009
TOP_RCM_PLL_CORE_MN2DIV [0x53200414] = 0x00000320
TOP_RCM_PLL_CORE_FRACDIV [0x53200418] = 0x08000000
TOP_RCM_PLL_CORE_HSDIVIDER_CLKOUT0 [0x5320042C] = 0x00000324
MSS_RCM_OSPI0_CLK_SRC_SEL [0x532081F0] = 0x00000333
MSS_RCM_OSPI0_CLK_DIV_VAL [0x532083F0] = 0x00000000

Can you please flash the SBL and hello world image attached and check once?

Also please see my sysconfig files.

After flashing the new images, please verify the reg values as well.

Thanks & Regards,

Aswin

Hi Aswin,

We programmed the SBL and application images provided from you (progress as below) on our custom board (referenced from TIDA-010979). It would not show any message from UART output under 4S boot mode. For uart boot mode, it outputs 'C' character every 3 seconds. By the way, the sbl_uart_uniflash_am261x-lp_r5fss0-0_nortos_ti-arm-clang.tiimage (flash writer) is modified and built by us based on different ISSI flash as TIDA-010979 than one used in LP-AM261 EVM board where the OSPI clock setting is as below snapshot for your reference.

python uart_uniflash.py -p /dev/ttyACM0 --cfg ./tida_orbit-ti/orbit-ti_sbl_app_TI_FAE.cfg

Parsing config file ...
Parsing config file ... SUCCESS. Found 3 command(s) !!!

Executing command 1 of 3 ...
Found flash writer ... sending ./tida_orbit-ti/sbl_uart_uniflash_am261x-lp_r5fss0-0_nortos_ti-arm-clang.tiimage

Sent flashwriter ./tida_orbit-ti/sbl_uart_uniflash_am261x-lp_r5fss0-0_nortos_ti-arm-clang.tiimage of size 95457 bytes in 8.73s.

Executing command 2 of 3 ...
Command arguments : --file=./tida_orbit-ti/sbl_ospi_multicore_elf.debug.tiimage --operation=flash --flash-offset=0x0
Sent ./tida_orbit-ti/sbl_ospi_multicore_elf.debug.tiimage of size 291740 bytes in 29.31s.
[STATUS] SUCCESS !!!

Executing command 3 of 3 ...
Command arguments : --file=./tida_orbit-ti/hello_world.debug.mcelf --operation=flash-sector-write --flash-offset=0x81000
Sent ./tida_orbit-ti/hello_world.debug.mcelf of size 53108 bytes in 7.71s.
[STATUS] SUCCESS !!!

All commands from config file are executed !!!

BR, Robert Huang

Hi Robert,

Apologies, the binary that I provided was based on AM261 EVM. So that flash part would be different. I was aiming to provide the files as an example in case you encountered some issue while setting the clock params in your application.

You can still check the sysconfig file provided. It can be opened in a TI System Configuration tool and the clock and OSPI properties can be checked.

Can you please ensure if the settings in provided sysconfig matches with that of yours?

Finally we want to make the register values( MSS and TOP RCM) aligned.