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AM13E23019: DMA Channel Priorities

Ari Mendes
Intellectual 495 points

Part Number: AM13E23019

Hi,

I didn't understand item 9.2.2 of the AM13E23019 Reference Manual. It says: "Transfers in progress are not halted if a higher-priority channel is triggered. The higher-priority channel waits until the transfer in progress completes before starting." So does this mean that if a DMA channel is transferring a large number of bytes to the UART, and an ADC trigger occurs on another DMA channel, even if that channel has higher priority, the data from the ADC will have to wait until all the bytes are transmitted by the UART before it can be transferred by DMA to memory?

Ari

  • +1
    TI__Mastermind 25070 points

    Hi Ari,

    Ari Mendes said:
    So does this mean that if a DMA channel is transferring a large number of bytes to the UART, and an ADC trigger occurs on another DMA channel, even if that channel has higher priority, the data from the ADC will have to wait until all the bytes are transmitted by the UART before it can be transferred by DMA to memory?

    Yes, that is correct. For this situation though, you should use a single transfer mode so that each transfer itself is only as big as the DMASRCWDTH value (8-bits, 16-bits, 32-bits, 64-bits, or 128-bits). That way each transfer itself is smaller and doesn't take as long as with a block transfer mode. With this, you can still set DMASZ to be something large to move over the full data, but the other channels don't have to wait for all of DMASZ. 

    Best Regards,

    Delaney