AM2634: AM2634COLFHAZCZR + DP83869 – Custom Board Schematic Review Request

Hi 

We will review from the MCU side, but PHY side schematics needs to be reviewed by the PHY team, please raise a seperate thread with PHY part number.

Hi Nilabh Anand

Thank you for your response.

We would like to request our TI team

Thank you

Hi,

We are currently reviewing, please allow some time for our feedback

Regards,

Peter

Hi,

We are still reviewing the design

Regards,

Peter

Dear Peter,

We have been eagerly waiting for your response regarding the schematic review.

We have a few questions and would appreciate your guidance:

1. Could you please confirm whether the reset mechanism implemented in our design is correct? Specifically, we would like to understand whether the PORz reset signal resets the entire controller and all associated peripherals after software configuration has been completed.
2. We are also looking forward to reviewing our software configuration with you. As discussed previously, we would like to verify that our Ethernet software configuration is aligned with the hardware design so that we can successfully achieve ping communication and proceed with Ethernet validation testing.

Your review and feedback on both the hardware schematic and software configuration would be greatly appreciated, as they are critical for our bring-up and debugging activities.

We look forward to your response.

Best Regards,
Phanendra 

Dear peter,
Please kindly respond on this . We are eagerly waiting on this

Hi Phanendra,

Thank you for your patience. Please see my comments

phanendra beella said:

1. Power Supply & Sequencing

• Are all voltage rails (1.1V / 1.8V / 3.3V) correctly designed?
• Is the power sequencing order correct for AM2634 and DP83869?
• Are decoupling capacitors correctly placed and valued?

For DP83869 you are intentionally supplying 1.2V which is slightly higher than the 1.1V input for the 1.1V rail, also 1.8V rail will be generated by PHY in 2-supply mode. 

phanendra beella said:

2. RGMII Interface

• Is RGMII signal connection between AM2634 DP83869 correct?
• Should we use internal delay or external delay on DP83869?
• Are series termination resistors required on RGMII lines?

The connections look fine, you should also enable the internal programmable termination impedance within the DP83869 RGMII. This depends on the board but if the trace lengths are not too long then this is sufficient

phanendra beella said:

3. Clock Network

• Is the 25MHz crystal circuit for DP83869 correctly designed?
• Are load capacitor values correct for the crystal?

Clock looks fine, you could possibly find a buffer which has reduced IOs since you are only using 2 outputs in your design. You may also add an optional connection in your design which leverages the CLKOUT0 signal from the AM2634 to drive the PHY CLK rather than requiring the clock buffer you can simplify the design by feeding the clock only to the AM2634 MCU

phanendra beella said:

4. PHY Strap Pin Configuration

• Is the PHY address strap pin configuration correct?
• Is RGMII mode correctly selected via strap pins?
• Is Auto-negotiation enabled by default?

This is something you will need to check with the PHY team, there is a calculator they provide which you can use to decide if the PHY strapping is accurate for all the functionality you require

phanendra beella said:

5. Reset Circuit

• Is the reset timing correct for both AM2634 and DP83869?
• Is the reset sequence proper between MCU and PHY?

I don't see where the RGMII1_RESETn signal is coming from in your design

phanendra beella said:

6. Boot Mode Pins

• Are AM2634 boot mode pins correctly configured?
• Any concerns with pull-up/pull-down values?

Was this part of the design changed from the previous revision? 

Regards,

Peter

Hi peter

Hi Peter,

For the RGMII1_RESETn signal, we are driving the RGMII reset using both the Warm Reset and PORz reset signals.

Could you please confirm whether there is any issue with providing 1.2V on the RGMII1_RESETn signal?

Apart from this, we hope the remaining design aspects are fine. We have been facing issues related to the RGMII interface, specifically with the TX/RX data and clock lines. We would appreciate your feedback on the reset implementation and any other observations you may have regarding our Ethernet design.

Thank you for your support.

Best regards,
Phanendra

Hi Phenandra,

I am currently out of office on business travel, I will help to answer your questions when I return to the office

Regards,

Peter

Hi,

I am currently returning from business travel and catching up on forum questions. I will get back to you shortly

Regards,

Peter

Hi Peter,

Could you please review our project Gerber files and PCB layout PDF attached with this email?

We would appreciate your feedback and confirmation before we proceed with PCB fabrication. If you have any observations or recommendations, please let us know so that we can incorporate them before releasing the design for manufacturing.

Thank you for being so supportive.
BLIS-CUST-_BLIS_CUSTOM_BOARD_REV03-29062026-172.pdf

Best regards,
Phanendra

Hi Phanendra,

I don't see many issues with the design from a layout perspective. Please see a few of my comments

• Verify proper integrated magnetics in Ethernet connector RJ45
• Partial bullet holing in between the MCU and PHY - offset vias to improve ground connection
• Verify trace length matching of DP DM signals

Regards,

Peter

Hi Peter,

Thanks for your confirmation on shared file . 
1. Already we have using suggested RJ45 from phy team if you any suggestion please let us know
2. We already did simulation for layout everything looks fine . if any thing please suggest on layout .
Please kindly confirm us for proceeding fabrication

Hi Phanendra,

I don't have any additional feedback for the design

Regards,

Peter

Hi Peter,

Thank you for your confirmation.  We will get back while testing

Thank you