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AM2431: Two 1-Bit Interrupts Triggered by a Single Error Injection

Qiao,Xue
Intellectual 280 points

Part Number: AM2431

I have enabled DDR inline ECC and, based on the error injection example code from SDK 12_00_00_26, I am able to successfully trigger a 1-bit ECC error interrupt.

However, I am observing that after injecting a single 1-bit error, two 1-bit error interrupts are generated.

Is this expected behavior?
My understanding is that only one interrupt should be triggered for a single error injection.

  • 0
    TI__Guru* 94181 points

    Yes that is what i would expect.  Read through section 8.1.4.3.3 ECC Statistics in the TRM (excerpt below).  Does the ECC_1B_ERR_CNT_REG only show 1 error?  There is also a 2-deep FIFO which shows the address location of the error.  Is this logging two separate addresses?  Maybe there are multiple one bit errors?

    See if you can get more information from the ECC stats to see if there is a reasonable explanation for what you are seeing.

    Regards,

    James