• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Subscribers 32 subscribers
  • Views 1074 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Can I pause MibSPI transmission with ENA?

Adam Crandall
Prodigy 45 points
Other Parts Discussed in Thread: TMS570LS20216, TMS570LS3137

Hi, all.

For MibSPI transmissions of multiple words with a TMS570 configured as the master in 5-pin mode, is the ENA pin supposed to be toggled by the slave device between each word being transferred?  If not, can the ENA pin be set by the slave device to pause data transfer once started?

Some background:
We are planning to have an FPGA communicate with TMS570LS20216 and TMS570LS3137 microcontrollers using the MibSPI peripherals (with the microcontrollers configured as masters).  The master will send a command to the FPGA (indicating size and address of data to read), and after some time the FPGA will respond with the requested data.  The time before the FPGA will have data available can vary, so we need to be able to support variable wait states.

Our desired use case is as follows: master sets CS low; slave sets ENA low; master sends command; slave sets ENA high; slave waits for requested data to become available; slave sets ENA low; slave sends data to master; slave sets ENA high; master sets CS high.  Unfortunately, we've been unable to determine from the documentation whether this functionality is supported by the ENA pin.  Per the TRM (spnu489c),
14.2: "Handshaking mechanism, provided by the SPIENA pin, enables a slave SPI to delay the generation of the clock signal supplied by the master if it is not prepared for the next exchange of data."
14.2.4: "If the SPIENA pin is in push-pull mode (ENABLE_HIGHZ = 0), the slave will drive SPIENA to 1 once it completes receiving a new character. The slave will drive SPIENA low again for the next word to transfer, after new data is written to the slave TX shift register."
14.2.13: "Note: When the chip select signal becomes active, no breaks in transmission are allowed. The next arbitration is performed while waiting for the time-out to occur."

If the ENA pin cannot be used, our backup plan is to define one transfer group for the command (master->slave) and a separate transfer group for the response (slave->master) to be triggered by a GIOA pin (set by the FPGA when its data is ready).

  • 0
    TI__Prodigy 550 points

    Adam,

    Yes, ENA pin is supposed to be toggled by the slave device between each word being transferred by writing to the shift register.

    The Slave can delay the generation of the clock signal supplied by the master with the help of the SPIENA. The slave needs to write to the shift register for every character length so as to read data from the master. Slave writing to the shift register enables the master clocks . If the slave stops writing to the shift register, the master will have to wait until slave is ready.

    section 14.2.5 explains in details the 5-pin mode of operation @ http://www.ti.com/lit/ug/spnu489c/spnu489c.pdf

  • 0 in reply to Sandeep R
    Prodigy 45 points

    Thank you for your prompt response.

  • 0 in reply to Adam Crandall
    Prodigy 45 points

    Just to be sure I'm on the right track, does the master also set its CS to 1 at the end of each word in 5-pin mode?  And if so, is this supposed to come before or after the slave sets its ENA (or does it matter)?

  • 0 in reply to Adam Crandall
    TI__Prodigy 550 points 
    Adam,
    CS, ENA are usually active low signals.
    In a 5-pin mode using both CS & ENA, the slave will drive the signal SPIENA low when new data is written to the slave shift register and the slave has been selected by the master (SPISCS is low).  If the slave 
    is deselected by the master (SPISCS goes high), the slave SPIENA signal is driven high. There can be many slaves & if the master selected a slave to talk to, then the slave can driver the flow control using ENA.
  • 0 in reply to Sandeep R
    Intellectual 480 points

    Hi all,

    I have similar problem as Adam but i have a different situation because I want to send data with DMA.

    So i want just to set everything (SPI with DMA and HW does transfer after ENA is set to low) and than the HW does it job.

    Protocol:

    Master sets CS low, sets DMA and HW wait for ENA to go low that can transfer, (interrupt GIO) Slave sets ENA low, sets DMA, send/recieve data, (interrupt DMA RX finish) Master set DMA and HW waits ena go low , (interrupt DMA RX finish) Slave ENA high,  prepare data, ENA low, send/recieve data,  DMA RX interrupt Ena high, CS high.

    (no toggle of ENA)

    Is there any possible configuration that on master side ENA signal just block transfer unitl ENA is high?

    I dont care about desync and timeout error.

    My slave side work perfect but master side is a problem. After Timeout flag is on than i never get BTC DMA interrupt or receive is finished.
    Settings ENA is functional, all time delay are 255u, data format  wait ena enabled = 1, and timers cs disabled = 1.

    First part of message is working, i get only desync flag (normal because ena is not toggling or each byte), second message i never get that DMA is finished and i see that desync and timeout flags are set.