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MSPM0C1106: Clarification on Cortex‑M0+ MPU Support in MSPM0C110x Devices

Part Number: MSPM0C1106
Other Parts Discussed in Thread: MSPM0C1105,

Hi there,

I am currently working on an application where I intend to utilize the Cortex‑M0+ MPU to protect multiple memory regions. The reference manual for the microcontroller indicates that MPU support is available within the MSPM0 family. However, the datasheet for the MSPM0C110x sub-family does not explicitly mention the absence of MPU resources, and I was also unable to find any details on the website regarding feature limitations by specific part numbers or packages.

Given this, I would like to request TI’s support to clarify whether the MSPM0C1105 and MSPM0C1106 devices are expected to support the Cortex‑M0+ MPU.

From my observations, the MPU_TYPE register returns all zeros, which suggests that no MPU is implemented. However, I would appreciate confirmation to ensure this is the expected behavior for these devices.

Best regards,
David M.