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AM2431: AM2431 – Register retention after WDT reset

Qiao,Xue
Intellectual 280 points

Part Number: AM2431

  We are currently working on fault diagnosis and would like to understand the behavior of register retention after a watchdog (WDT) reset on the AM2431 device.
  Our requirement is to determine whether it is possible to preserve a small piece of information (for example, a fault flag) across a WDT-triggered reset, so that it can be read after the system restarts.
 
 We would like to confirm the following:
1.Are there any registers in AM2431 that retain their values after a WDT reset (warm reset)?
2.Are there specific reset types (e.g., MCU reset vs MAIN reset) that affect register retention differently?
 
Any guidance or reference to relevant sections of the TRM would be greatly appreciated.
  • 0
    Intellectual 280 points
    Let us provide additional details about our usage scenario. ECC is currently enabled for Cortex‑R5F memory, OCSRAM memory, and DDR. When a double‑bit error occurs, the system resets immediately. After the reboot, we would like to identify which of these three ECC sources triggered the WDT reset.
  • 0 in reply to Qiao,Xue
    TI__Intellectual 1380 points

    Hello Qiao,

    If you want more information about the reset, you can review the AM243 TRM, section 5. Device Configuration, point 5.3 Reset.

    Qiao,Xue said:
    1.Are there any registers in AM2431 that retain their values after a WDT reset (warm reset)?

    You can read these articles for additional information about resets:

    AM2434: Retaining variables in RAM across warm reset.

    [FAQ] AM625 / AM623 / AM620-Q1 / AM625-Q1 / AM62Ax / AM62D-Q1 / AM62Px / AM64x / AM243x (ALV, ALX) Design Recommendations / Custom board hardware design - Processor Reset inputs, Reset Status Outputs and Connection Recommendations

     

    Qiao,Xue said:
    2.Are there specific reset types (e.g., MCU reset vs MAIN reset) that affect register retention differently?

    The MCU and MAIN domains can be configured to have independent warm reset pins via software. MCU_RESETz and RESETz_REQ. By default, these two pins have the same effect and will act as a warm reset source for both MAIN and MCU domains. When the MCU domain is configured for reset isolation, MAIN domain resets will only reset the MAIN domain and the MCU domain will remain unaffected by all MAIN domain resets.

    Best Regards,

    Borislav Lazarkov

  • 0 in reply to Borislav Lazarkov
    Intellectual 280 points

    Thank you for your response.

    I am currently trying to directly access the M4F RAM from the R5F. However, it seems that the M4F RAM region is not accessible.

    Are there any additional settings required to enable this access?
    Is it mandatory to use IPC for this purpose?

    My code is as follows. When the code [*p = write_val;] is executed, it jumps to address 0x10.

    void test_ram_rw(void)
    {
    uint32_t write_val = 0x12345678;
    uint32_t read_val = 0;
    uint32_t addr = 0;

    DebugP_log("RAM RW test start\n");
    addr = (uint32_t)AddrTranslateP_getLocalAddr(CSL_MCU_M4FSS0_IRAM_BASE);

    volatile uint32_t *p = (volatile uint32_t *)addr;

    *p = write_val;
    read_val = *p;

    if (read_val == write_val)
    {
    DebugP_log("PASS: write OK, read = 0x%08x\n", read_val);
    }
    else
    {
    DebugP_log("FAIL: read = 0x%08x\n", read_val);
    }
    }
  • 0 in reply to Qiao,Xue
    Intellectual 280 points

    I suspect that the address CSL_MCU_M4FSS0_IRAM_BASE may be an invalid address. The jump to 0x10 happens to correspond to the Data Abort vector address.

    I would like to confirm the following points:

    1. The current return value of the function Bootloader_socIsMCUResetIsoEnabled is 0, which indicates that the MCU is not enabled. In this state, will the MCU RAM also be cleared after a reset?

    2. To achieve my intended behavior, should I configure pscMain2MCUDisable = 0 and pscMCU2MainDisable = 1, and ensure that Bootloader_socIsMCUResetIsoEnabled returns 1?

  • 0 in reply to Qiao,Xue
    TI__Intellectual 1380 points

    Hello Qiao,

     Would you please clarify the address CSL_MCU_M4FSS0_IRAM_BASE? What does IRAM in the name stands for - Instruction RAM or Internal RAM? If it is instruction RAM and you can not access it, why don't you try with M4 Data RAM - DRAM?

    Best Regards,

    Borislav Lazarkov

  • 0 in reply to Borislav Lazarkov
    TI__Intellectual 1380 points

    Hello Qiao,

     Do you use AM64x/AM243x Linux SDK or MCU + SDK ? Which version of the SDK you are using ?

    Best Regards,

    Borislav Lazarkov