SCI transmit problem

Dave,

Here is my analysis of your code and the reasons of your problem.

In your init routine, you start setting the swreset bit to 0 in GCR1. This is correct.
Then you configure all other bits in GCR1 and also set the software reset bit to 1.

Later you change the baud rate  and the data format.
This is not recommended. All SCI configurations have to be done with the SCI in reset.

When everything is set, than you can write the swreset bit to 1.

  sciREG1_SG->GCR1 = ( 1 << 25 ) /* Enable transmit */

                     | ( 1 << 24 ) /* Disable receive */

                     | ( 0 << 17 ) /* Disable continue on suspend */

                     | ( 0 << 16 ) /* Disable loop back mode */

                     | ( 0 << 10 ) /* Disable multi-buffer mode */

                     | ( 0 << 8 )  /* Disable sleep mode */

                     | ( 1 << 7 )  /* Stay in reset state to allow configuration */

                     | ( 0 << 6 )  /* LIN mode is disabled SCI mode is enabled */

                     | ( 1 << 5 )  /* Use internal clock */

                     | ( 0 << 4 )  /* 1 stop bits */

                     | ( 1 << 3 )  /* Even parity */

                     | ( 0 << 2 )  /* Disable parity */

                     | ( 1 << 1 )  /* Asynchronous timing */

                     | ( 0 );       /* Do not use address bit */

  sciREG1_SG->GCR1 = ( 1 << 25 ) /* Enable transmit */

                     | ( 1 << 24 ) /* Disable receive */

                     | ( 0 << 17 ) /* Disable continue on suspend */

                     | ( 0 << 16 ) /* Disable loop back mode */

                     | ( 0 << 10 ) /* Disable multi-buffer mode */

                     | ( 0 << 8 )  /* Disable sleep mode */

                     | ( 0 << 7 )  /* Stay in reset state to allow configuration */

                     | ( 0 << 6 )  /* LIN mode is disabled SCI mode is enabled */

                     | ( 1 << 5 )  /* Use internal clock */

                     | ( 0 << 4 )  /* 1 stop bits */

                     | ( 1 << 3 )  /* Even parity */

                     | ( 0 << 2 )  /* Disable parity */

                     | ( 1 << 1 )  /* Asynchronous timing */

                     | ( 0 );       /* Do not use address bit */

  /* Setup baud rate to 4800 BAUD register AKA BRS - Baud Rate Selection Register */

  sciREG1_SG->BAUD = 650U;

  /* Setup data transmission length */

  sciREG1_SG->FORMAT = 7U;

And than

  /* Start the SCI */

  /* Take SCI/LIN out of reset state to allow operation */

  sciREG1_SG->GCR1 |= ( 1 << 7 ); 

There is another point I want to highlight.
Once the SCI is released from reset, with a valid configuration, (baudrate, character length…) the SCI needs to synchronize.

Bit 2 IDLE. SCI receiver in idle state.

While this bit is set, the SCI looks for an idle period to resynchronize itself with the bit stream. The receiver does not receive any data while the bit is set. The bus must be idle for 11 bit periods to clear this bit. The SCI enters this state if one of the following events occurs: a system reset, an SCI software reset, power down, and if the RX pin is configured as a general I/O pin.

0=Idle period detected, the SCI is ready to receive.
1=Idle period not detected, the SCI will not receive any data.

This bit is located in the SCIFLR register. If you don’t wait for this bit to be cleared, the SCI cannot receive any data, but it can still send data.
The absolute time is directly linked to your baudrate and character length.

In our driver (HalcoGen) there is no waiting loop for this bit to be cleared in the SCI Init routine. Usually, the application code will have to check this bit before attempting to send any data.

Again, in your case it is not an issue, you are just sending data.
For reference, this is what you can do:

while ((sciREG1_SG->FLR&0x4)==0x4);   //Wait for IDLE bit to be cleared.

Please let me know if this will fix your problem.

Best Regards,

Jean-Marc