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VIC code in HALCoGen for TMS570?

Marco Moreno
Intellectual 300 points 


Hi,


I was looking at the sys_startup.c file for the TMS570 as generated by HALCoGen and noticed a call to this function:




_coreEnableIrqVicOffset_

        mrc   p15, #0, r0,         c1, c0,  #0
        orr   r0,  r0,    #0x01000000
        mcr   p15, #0, r0,         c1, c0,  #0
        bx    lr

    .endasmfunc




Seeing as there is no VIC on the TMS570, is this an unnecessary init function or is there something going on here that the function naming does not represent?




Thanks,


Marco

								


				
				

				
			

		

			
						
									
                			    			            
						
						
			
			
			
			                        
			

				

			


			

		


				    			

						

















	

	

					
    
	
    





		
	
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                          TI__Mastermind
                        22375 points
                      
    
                          
                   		
		
    
					
    

    Marco,
    

    

    Document SPNU499 on page 610 (15.2.3 Software Interrupt Handling Options) describes the 3 different mode of operation for the VIM.
    Option 3 Hardware vectored interrupt behavior must be explicitly enabled by setting the vector enable (VE) bit in the CP15 R1 register.
    

    This is the purpose of  the _coreEnableIrqVicOffset_ routine.
    

    Please let me know if I've answered your question.
    

    

    Thanks and Regards,
    

    Jean-Marc
    
			
    

		
		
		
		
	
    
	
    
		
    
			
		
    
	
    

	            
                 	
	
    
				
		                
                
                
                
                
                
                
        		
		
				
    
			
		
    
		
		 
		
		
     
    
	
    

    
			
    
			
    
		
    

		
    
	
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