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AM625-Q1: AM625: DDR SysConfig Configuration Issues

z ryan
Prodigy 90 points

Part Number: AM625-Q1
Other Parts Discussed in Thread: SYSCONFIG, AM625

  1. We use the SysConfig tool to configure DDR memory, which generates the k3-am62x-sk-ddr4-1600MTs.dtsi device tree include file.
  2. Our configuration parameters:
    • Memory Frequency (MHz): 800
    • Data Bus Width (per device): 8
    • Read DBI: Disabled
    • CL (CAS Latency): 12
Issue:
 
Some boards crash during memtest, specifically failing in the Solid Bits and Bit Flip test items. Adjusting CL from 9 to 12 has improved stability, but we need guidance on tuning other parameters. All remaining parameters are currently configured strictly according to the DDR chip datasheet.
Request:
 
Is there any official tool that can automatically scan and recommend the required parameters for SysConfig configuration? Or what is the standardized/recommended methodology to properly calibrate these DDR parameters for optimal stability on the AM625 platform?
  • 0
    TI__Guru* 94451 points

    Hi, 

    which DDR4 are you using?  Can you provide part number and/or datasheet?

    -Can you provide the full configuration from the SysConfig tool (.syscfg file)?

    If your DDR4 supports Read DBI, you should enable this and set CL=14.  

    Regards,

    James

  • 0 in reply to JJD
    Prodigy 90 points

    Memory Part Number: IS46QRB1024A
    Read DBI is not supported

  • 0 in reply to JJD
    Prodigy 90 points

    hello

    Memory Part Number: IS46QRB1024A
Read DBI is not supported.


LPASR mode: Manual mode, Normal temperature
TCR mode: Disabled
TCR range: Normal
CL (CAS Latency, nCK): 12
CWL (CAS Write Latency, nCK): 9
CA Parity Latency: Disabled

DRAM Timing B) Timing Parameters
tCCD_L (tCK): 5
tCCD_L (ns): 6.25
tCCD_S (tCK): 4
tCKE (tCK): 3
tCKE (ns): 5
tCKSRE (tCK): 5
tCKSRE (ns): 10
tCKSRX (tCK): 5
tCKSRX (ns): 10
tDLLK (tCK): 597
tDQSCKmax (ns): 0.22
tFAW (tCK): 20
tFAW (ns): 25
tMOD (tCK): 24
tMOD (ns): 15
tMRD (tCK): 8
ODTH8 (tCK): 6
tPAR_ALERT_PWmax (tCK): 96
tPW_RESET_L (ns): 200000
tRAS (ns): 32
tRCD (ns): 14.16
tREFI (ns): 7800
tRFC (ns): 350
tRP (ns): 14.16
tRRD_L (tCK): 4
tRRD_L (ns): 6
tRRD_S (tCK): 4
tRRD_S (ns): 5
tRTP (tCK): 4
tRTP (ns): 7.5
tWR (ns): 15
tWR_CRC_DM (tCK): 4
tWR_CRC_DM (ns): 3.75
tWTR_L (tCK): 4
tWTR_L (ns): 7.5
tWTR_S (tCK): 2
tWTR_S (ns): 2.5
tWTR_S_CRC_DM (tCK): 4
tWTR_S_CRC_DM (ns): 3.75
tXP (tCK): 4
tXP (ns): 6
tXPR (tCK): 5

IO Control A) Processor / DDR Controller IO Configuration
VREF Control Range DQ/DM: Range 1
VREF Control % of VDDQ DQ/DM: 72.8
Driver Impedance for DQ/DQS/DM: 48 Ohm
Driver Impedance for Addr/Ctrl/Clk: 48 Ohm
ODT for DQ/DQS/DM: 60 Ohm

IO Control B) DRAM IO Configuration
DQ VREF Range: Range 1
DQ VREF: 72.4
Output Driver Impedance (ODI): RZQ/5 (48 Ohm)
Nominal ODT (RttNOM): RZQ/4 (60 Ohm)
Dynamic ODT: Disabled

  • 0 in reply to JJD
    Prodigy 90 points

    Configuration Details
    Memory Frequency 800
    Data Bus Width  8
    Density 16
    Chip Selects / Ranks: 1
    Read DBI: Disabled

  • 0 in reply to z ryan
    TI__Guru* 94451 points

    Density setting is per device.  Since you are using 2 x8 devices 1Gx8, it should be set to 8, not 16.  Try running your tests with this change.

    Regards,

    James

  • 0 in reply to JJD
    Prodigy 90 points

    Hello, please respond to my question

  • 0 in reply to z ryan
    TI__Guru* 94451 points

    We recommend performing board level SI simulations to come up with optimal IO parameters for your DDR configuration.  Using the Sysconfig tool and inputting the parameters from the datasheet will provide the best configuration for the DDR controller to perform initialization and training.

    Regards,

    James