Part Number: AM2431
Hi TI team,
We are using AM243x with inline DDR ECC and would like to confirm best practice for 1-bit errors.
We are currently using with only one core enabled, and we have set the 1-bit ECC interrupt priority to 0.
I reviewed your previous response
PROCESSOR-SDK-AM62X: DDR ECC Single Bit Error Correction Guideance - Processors forum - Processors - TI E2E support forums
and would like to confirm the following:
1.In this AM243x single-core setup, do you still recommend not writing corrected 1-bit data back to physical DRAM?
2.If we do not write corrected data back to DDR, a 1-bit ECC error will occur every time this address is read.
For this repeated error behavior, do you have any recommendations?
