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MSPM0L1117: BOOTRST reset don't reset SRAM memory

Kostadin Karaivanov
Prodigy 51 points

Part Number: MSPM0L1117
Other Parts Discussed in Thread: MSPM0G3507, MSPM0L1306

Hello,

We are using the MSPM0L1117. We are performing a watchdog reset and expecting the SRAM to be reset as described in the processor's datasheet. The WWDTLP0RSTDIS register is set to 0. However, the behavior is as follows: The controller resets, but the SRAM retains its variables, as well as the no-init variables.

Regards,

Kostadin

  • 0
    TI__Mastermind 30610 points

    Hey Kostadin,

    I don't fully understand the expectoration here.  Are you expecting the BOOTRST to set all of SRAM to a certain value?  As far as I'm aware, SRAM has no reset value and after a power cycle, comes up in random, unknown states.  Application code (or really the compiler/linker) must initialize a variable in SRAM to a know value before it is used.   

    In the case of data being in SRAM, SRAM remains powered but the CPU resets, I expect the contents of SRAM to still be there.  There was no power-cycle of the memory.   I don't expect the application code to know or trust the values that are there and to re-initialize the memory as needed.   

    Hope this helps,

    JD

  • 0 in reply to JD Crutchfield
    Prodigy 51 points

    Hello JD,

    Let me provide more details.We are using IAR Embedded Workbench version 9.6 and working with both the MSPM0L and MSPM0G microcontroller series.Both projects are running on official TI LaunchPads.

    We are using uninitialized RAM (no-init memory) in both series. According to the "Reset Cause Encoding" table in the datasheets (attached is a screenshot from the MSPM0L datasheet), a watchdog (WDG) reset should trigger a BOOTRST, which clears all RAM. However, we are observing two different behaviors:

    • MSPM0G series: After a WDG reset, the no-init memory is cleared as expected.

    • MSPM0L series: The no-init memory is not cleared after a WDG reset.

    In both projects, the WWDTLP0RSTDIS bit is set to 0, which should ensure a BOOTRST execution.

    Is this a known errata/limitation for the MSPM0L series, or is there a specific startup file / linker configuration change required in IAR 9.6 to prevent/ensure RAM clearing on WDG reset for this specific MCU?

  • 0 in reply to Kostadin Karaivanov
    TI__Mastermind 30610 points

    Hello Kostadin,

    I've dug more into this for you. As I mentioned, generally SRAM is not initialized in that when it is "reset" or power-cycled has no guaranteed starting state.  This is also mentioned in this note of the TRM.  When you compiler your code, any initialized variable in SRAM will be configured by some runtime startup code that runs before you reach main().  

    In your case, the MSPM0L1306 is operating how I would expect and it's MSPM0G3507 that I'm surprised that the SRAM has been "cleared." which I interrupt as being written all 0x00. 

    I spoke with team, and learned that this is an expected difference between MSPM0's with no SRAM parity/ECC (MSPM0L1306) and devices that do have parity/ECC (G3507).  On the devices with Parity or ECC, we actually did add hardware initialization to SRAM so that you wouldn't immediately get parity/ECC errors if you accessed it as mentioned in that above TRM note.  On devices without ECC, this hardware initialization is not added and these devices continue to have random SRAM values. 

    Hopefully this clarifies this behavior you are observing.  Let me know if you have any additional follow-up questions. 

    Thanks,

    JD  

  • 0 in reply to JD Crutchfield
    Prodigy 51 points

    Hello JD,

    The MCU behaviour is clear, however I would appreciate some additional guidelines and clarification.

    We want to execute the Watchdog test and to store some "magic" number. As per my understanding the only way to do that is to use SHUTDOWN registers, is that correct?

    This "magic" number is usually stored in the no-initialized memory, however in this particular occasion all available memory is cleared by the hardware. With that being said, what are the alternatives to skip some SRAM region and to use it for the no-initialized memory?

    Appreciate your explanation and guidelines on the process.

    Thank you,

    Kostadin

  • +1 in reply to Kostadin Karaivanov
    TI__Mastermind 30610 points

    Hello Kostadin,

    So, It seems like it would depend on which WDT is used.  TRM states the Shutdown resisters are reset in a POR, but not in a BOR or lower reset.  

    WWDT0 and WWDT1 trigger Bootrst or Sysrst, but the IWDT (if it is on the specific device) triggers a POR reset which would reset the shutdown registers.

    If you need it to persist through a POR, then we would have to store the magic number in Flash, but it seems that is not wanted in this case.  

     

    Thanks,

    JD