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AM2434: AM243x: Alternative GPIO Pin Selection for EtherCAT PHY Reset (tiesc_addOnBoardResetSequence)

sahar schwartz
Prodigy 150 points

Part Number: AM2434
Other Parts Discussed in Thread: SYSCONFIG

Hi,

According to the EtherCAT SubDevice ICSSG0 Usage Guide document (https://software-dl.ti.com/processor-industrial-sw/esd/ind_comms_sdk/am243x/2026_00_00_06/docs/am243x/ethercat_subdevice/_i_c_s_s_g0__usage__guide.html), the GPIO_RESET_ICSS0_PHY1 and GPIO_RESET_ICSS0_PHY2 signals are expected to be assigned to pins GPMC0_CLK / R17 and GPMC0_ADVn_ALE / P16.

In our custom board design, these specific GPMC pins are already allocated for other functionalities.

I would like to know, where should we we map these PHY reset signals? is it the ECAT_IN_nRST and ECAT_OUT_nRST?

Thanks!

  • 0
    TI__Genius 12130 points

    Hello Sahar,

    The Control Module pad-configuration topic owner is back from his holiday on June-17. 

    Please expect his follow-up answer by June-18 COB.

    Thank you !

    Best Regards,

    Anastas Yordanov 

  • 0
    TI__Guru 50931 points
    sahar schwartz said:
    he GPIO_RESET_ICSS0_PHY1 and GPIO_RESET_ICSS0_PHY2 signals are expected to be assigned to pins GPMC0_CLK / R17 and GPMC0_ADVn_ALE / P16.

    These are board dependent signals and nothing ESC specific  - you can technically map any free GPIOs here

  • 0 in reply to PratheeshGangadhar
    Prodigy 150 points

    Hi

    Thank you for your response.

    can you be more specific? just assign any 2 pins under the names GPIO_RESET_ICSS0_PHY1 and GPIO_RESET_ICSS0_PHY2? how will it have any effect?

    Sahar

  • 0 in reply to sahar schwartz
    TI__Genius 13375 points

    Hi Sahar,

    To directly answer your follow-up, here is exactly how the pin assignment works end-to-end.

    Current EVM SysConfig configuration:

    The SDK example configures two GPIO instances in SysConfig for PHY reset:

    SysConfig Name Physical Pin Direction Default Value Pull
    CONFIG_GPIO_31 GPMC0_CLK / R17 Output 0 (reset asserted) No Pull
    CONFIG_GPIO_32 GPMC0_ADVn_ALE / P16 Output 0 (reset asserted) No Pull

    These are the two pins your board cannot use.

    How it connects to the PHY reset circuit

    The signal path is:

    SoC GPIO (GPMC0_CLK / GPMC0_ADVn_ALE) with respect to the add-on board schematic:
  → AND gate combined with MCU_PORz
  → PHY0_RESET_N / PHY1_RESET_N
  → DP83826 RST_N (pin 32)

    A 10 kΩ pull-down on the GPIO input side of the AND gate ensures the PHY stays held in reset at power-up. The default value of 0 in SysConfig means the GPIO initializes low (reset asserted) until tiesc_addOnBoardResetSequence() runs the toggle sequence.

    What to change on your custom board

    1. In SysConfig, keep the two GPIO instances named exactly CONFIG_GPIO_31 and CONFIG_GPIO_32 . The software uses those names.
    2. Change only the GPIO Peripheral pin assignment from GPMC0_CLK/R17 and GPMC0_ADVn_ALE/P16 to any two free GPIO-capable pins on your device.
    3. Keep all other settings identical: Direction = Output, Default Value = 0, Pull = No Pull.
    4. Regenerate the sysconfig files to match your new pins.
    5. On the hardware side, route those new SoC pins to your DP83826 (or any PHY being used) RST_N lines (ideally through the same AND gate + pull-down pattern from the reference schematic for safe power sequencing).

    No changes to tiescsoc.c:561-574 are needed. I hope you have the schematic for the add-on board.

    Regards,
    Aaron