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TMS570LS3137: Startup and Denial Of Service enhancement upon MCU failures

Marc Cifuentes
Intellectual 280 points

Part Number: TMS570LS3137

Hello,

Based on project demo and recommandations, we implemented a startup sequence for our SW, which contains some test to verify primary MCU function (CPU, PBIST,..) are correctly working before starting our application.

For a couple of those tests (see below), in case of a failure, we implemented an infinte loop reaction to avoid further application to run, without reset mechanisms.

In order to enhance our SW and avoid as much as we can kind of "Denial Of Service" (because of those infinite loop in case of failure), I'd like to know if you are any recommendations how to handle those failures, or could we continue the application to start (when possible) ? (log warning otherwise,...)

Here are the concerned test at MCU startup : 

  • PLL failures : _errata_SSWF021_45_both_plls(PLL_RETRIES) != 0U.
  • ESM Group 3 error
  • PINMUX register : write and read test.
     
  • STC & CPU selftest.
     
  • PBIST SRAM, STC ROM, ROM selftest.
  • CCMR4F self test : (CCMR4F_SELF_TEST/CCMR4F_ERROR_FORCING_TEST/
    CCMR4F_SELF_TEST_ERROR_FORCING)
     
    Thank you !
     
    Regards,
     
    Marc

 

 

  • +1
    TI__Guru* 78756 points

    Hi Marc,

    Marc Cifuentes said:
    I'd like to know if you are any recommendations how to handle those failures, or could we continue the application

    The answer depends on the safety criticality of the failed hardware element and your safety goal / ASIL level. Here is a test-by-test analysis:

    Marc Cifuentes said:
    PLL failures : _errata_SSWF021_45_both_plls(PLL_RETRIES) != 0U.

    Recommendation: Do NOT continue. Trigger a safe state (reset or safe shutdown).

    • The PLL is the clock source for the entire MCU. A PLL failure means the CPU and peripherals may run at an incorrect or unstable frequency.
    • The errata workaround already includes retries (PLL_RETRIES). If all retries are exhausted, the hardware is genuinely faulty.
    • Alternative to infinite loop: Instead of an infinite loop, trigger a system reset (via SYS_ECR register) or assert a safe state output.
    Marc Cifuentes said:
    ESM Group 3 error

    Recommendation: Do NOT continue. This is a hard fault — trigger reset or safe state.

    • ESM Group 3 errors are high-severity, non-maskable errors (e.g., CPU self-test failure, memory ECC double-bit errors). They are designed to be unrecoverable.
    • Alternative to infinite loop: Assert the nERROR pin (which the ESM does automatically for Group 3), and perform a CPU reset or hold in safe state. The external safety monitor (if present) should detect the nERROR assertion.
    Marc Cifuentes said:
    PINMUX register : write and read test

    Recommendation: Depends on which pins failed. Consider degraded-mode operation with logging.

    • A PINMUX failure means a specific I/O multiplexer register is not behaving correctly.
    • If the affected pin is not safety-critical (e.g., a debug UART), you may log a warning and continue with reduced functionality.
    • If the affected pin is safety-critical (e.g., a PWM output controlling an actuator, or a communication bus for safety data), treat it as a hard fault → reset or safe state.
    • Recommendation: Classify your PINMUX registers by criticality at design time, and implement selective failure handling accordingly.
    Marc Cifuentes said:
    • STC & CPU selftest.
       
    • PBIST SRAM, STC ROM, ROM selftest.
    • CCMR4F self test : (CCMR4F_SELF_TEST/CCMR4F_ERROR_FORCING_TEST/
      CCMR4F_SELF_TEST_ERROR_FORCING)

    Recommendation: Do NOT continue. Trigger reset.

    similar to the PLL failures.
    --
    Thanks & regards,
    Jagadish.