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DCC - Error Interrupt

Other Parts Discussed in Thread: HALCOGEN

Hello,

I've configured in HalCoGen 3.0 the module DCC1 such that:

Clock Source 0 is HF_LPO    10 MHz

Clock Source 1 is PLL1          160 MHz

Count 0 is 49005

Count 1: 792000

Valid 990

Additionally is enabled DCC, Enable Done Interrupt, Enable Error Interrupt and Enable Single Shot Mode. I also set the VIM channel 82 and 83, generated code, etc.

This configuration generates Done Interrupt as expected. In the next step I modified in code the value of Count 0 to 495, which should generate the Error Interrupt. In fact, I can observe that 0-bit of the DCC status register is 1 and the rest is zero, but no interrupt arrived.

Has anybody an idea why the error interrupt was not triggered?

Thank you

 Vaclav

  • Hello Vaclav,

    The VIM channels 82 and 83 are for the "Done" states for the two DCC modules supported on this microcontroller.

    The DCC1 error signal is mapped to the Error Signaling Module's group1 channel 30. You need to enable interrupt generation for this ESM group1 channel using the ESMIESR1 register at address 0xFFFFF508.

    The DCC2 error signal is mapped to ESM group1 channel 62, and you would use ESM control register ESMIESR4 for enabling an interrupt for a DCC2 Error condition.

    Regards, Sunil

  • Hello Sunil,

    Thank you for your helpful reply.

    By the way, the chapter 11 "Dual-Clock Comparator Module" from SPNU499 September-2011 is not describing the error signalling mechanism you mentioned. I guess that I'm not using the right document for these topics. Could you point me to the source of information where I can find such details?

    Thank you

    Vaclav 

  • Hello Vaclav,

    The SPNU499 document is a reference manual that describes the behavior of each individual IP block on the microcontroller. The mapping of interrupts and error signals is usually described in the specific part's datasheet. You can find the datasheet for the part that you are using here.

    Regards, Sunil