Part Number: AM2434
Dear TI Support,
For an AM2434 MCU, I would like to periodically verify that ECC error detection is functioning reliably.
For the cache memories, the SDK example project (r5_ecc_cache_app_am243x-evm_r5fss0-0_nortos_ti-arm-clang) works as expected. However, it only tests the cache memories (RAM_ID 0–20), and the TCM memories (ATCM and BTCM) are not covered by this example.
The TCM memories also cannot be tested using the ecc_app_am243x-evm_r5fss0-0_nortos_ti-arm-clang project.
While analyzing the SDL_ECC_selfTest() API, I noticed that for TCM memories the error detection is based on the CP15 CFLR register. Is this the expected mechanism for detecting ECC errors in TCM, or should the errors instead be detected through the Event Bus?
Is there currently any example project that demonstrates how to inject and detect ECC errors in the TCM memories?
Could you also clarify what the recommended procedure is for ECC error injection and detection in TCM memories?
What is the recommended procedure for clearing an ECC error and repeating the error injection?
For example, the SDL_ECC_selfTest() API appears to work only once. After the first execution, it is no longer possible to inject another ECC error into the same TCM memory.
From my investigation, the API does not clear the CP15 CFLR register. Even if I manually clear the CFLR register, I still cannot inject another ECC error.
Could you please clarify the correct sequence of steps required to:
- clear the previous ECC error,
- reset the ECC error status, and
- perform another ECC error injection on the TCM memory?
Is there any additional register, cache/TCM maintenance operation, or CPU reset sequence that must be performed before another ECC self-test can be executed?
SDK version(s) used:
mcu_plus_sdk_am243x_08_06_00_43__all
mcu_plus_sdk_am243x_11_00_00 - this is the currently used
mcu_plus_sdk_am243x_12_00_00_27
Thank you for your assistance.
Best regards,
Balázs Hegyi
