AM2434: AM2434 - R5FSS -TCM - ECC - error injection

Hi,

Balazs Hegyi said:

Is this the expected mechanism for detecting ECC errors in TCM, or should the errors instead be detected through the Event Bus? 

Yes, ECC for both TCMs and Cache memories R5F maintains the ECC mechanism. 

Balazs Hegyi said:

Is there currently any example project that demonstrates how to inject and detect ECC errors in the TCM memories?

Currently there's no example for AM243x. It's being planned for the next release. However, we have reference example in AM62Ax. You can use that as a reference for AM243x.

https://github.com/TexasInstruments/mcupsdk-core-k3/tree/k3_next/examples/sdl/ecc_tcm/am62ax-sk/mcu-r5fss0-0_nortos

Since it's the R5F core is the same, the code should be very similar.

Regards,

Nihar Potturu

Hello Nihar Potturu,

Thank you for your quick response. I apologize, as my question was not entirely clear, and therefore the answer was not completely clear to me either.

Am I correct in understanding that TCM and cache errors are only available via the Cortex-R5F internal error/status registers and are not exported to the event bus? 

 I am checking the example

Many thanks
Balázs Hegyi

Hi,

Balazs Hegyi said:

Am I correct in understanding that TCM and cache errors are only available via the Cortex-R5F internal error/status registers and are not exported to the event bus? 

You are partially correct. The errors are reported by R5F core directly, but they are also routed to the SoC ESM. The TCM errors would be reported through the same ESM event as the R5F Cache memories. 

Regards,

Nihar Potturu

Balazs Hegyi said:

 I am checking the example

I am attaching the example that will be added in the next release for AM243x below. You can take a look at that instead.

ecc_tcm.zip

Regards,

Nihar Potturu

Thank you for sending the example code. I ran it, and the example works as expected. However, I am still experiencing an issue when trying to perform repetitive ECC testing.

I am unable to trigger the error again. This issue is also reproducible with the example code you provided after making the following modification:

int32_t ECC_funcTest(void)
{
    int32_t testResult;

    testResult = ECC_Example_init();

    if (testResult != SDL_APP_TEST_PASS)
    {
        DebugP_log("\r\nECC Safety Example tests: unsuccessful\r\n");
        return SDL_EFAIL;
    }

    testResult = ECC_sdlFuncTest();

    if (testResult == SDL_APP_TEST_PASS)
    {
        DebugP_log("\r\nECC Test Round 1 completed successfully. \r\n");
        testResult = ECC_sdlFuncTest();
    }

    return (testResult);
}

ECC TCM Example Application

ECC_Example_init: Initializing MAIN ESM.

ECC_Example_init: Init MAIN ESM complete 


 AGGR ECC Init complete 

ECC Safety Example tests: starting

 B0TCM0 Bank0 Double bit error inject test: starting
 B0TCM0 Bank0 Double bit error inject test: pErrMem 0x41010000 fixed location once test complete
Waiting for ESM Interrupt

UC-1: Got High priority ESM Interrupt 

B0TCM0 Bank0 Single bit error inject test: starting

B0TCM0 Bank0 Single bit error inject test: at pErrMem 0x41010000: fixed location once test complete
Waiting for ESM Interrupt

UC-2: Got Low priority ESM Interrupt

ECC Safety Example tests: success

ECC Test Round 1 completed successfully. 

ECC Safety Example tests: starting

 B0TCM0 Bank0 Double bit error inject test: starting
 B0TCM0 Bank0 Double bit error inject test: pErrMem 0x41010000 fixed location once test complete
Waiting for ESM Interrupt

ESM_ECC_Example_run: UC-1 has failed...

ECC Safety Example tests: failed

ECC UC-1 and UC-2 Test

Some tests have failed. 

My question is: how can the ECC error be triggered again?

Many thanks
Balázs Hegyi

One additional observation: the dual-bit error test can be repeated consecutively any number of times without any issues. However, once the single-bit error test has been executed, neither the dual-bit nor the single-bit error test can be run again.

Hi,

Apologies for the delay here. 

Balazs Hegyi said:

One additional observation: the dual-bit error test can be repeated consecutively any number of times without any issues. However, once the single-bit error test has been executed, neither the dual-bit nor the single-bit error test can be run again.

This is an expected behaviour. This is a limitation of R5F core. Once an SEC error occurs at a particular address, unless another error is injected at a different address, any subsequent errors at the initial address will not be reported. Attaching screenshot from ARM documentation below:

Balazs Hegyi said:

My question is: how can the ECC error be triggered again?

It should be sufficient to perform the error injection test once. Any reason for trying to execute it multiple times?

Regards,

Nihar Potturu

We are required to periodically verify the reliable operation of ECC error detection. Therefore, I am considering periodic ECC error injection.

Is there an officially recommended alternative method for confirming that ECC error detection is operating correctly?

Hi,

You can have two different addresses for error injection tests and alternate between them every time so that the issue is not seen. 

Regards,

Nihar Potturu