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AM2634: AM2634 Queries

TEMC
Expert 1015 points

Part Number: AM2634

1. UART: 

Original query: Whether the line status regsister (UART_LSR) 6th bit corresponding to shift register can be mapped to any interrupt ? 

TI reply: TX_EMPTY_CTRL_IT bit in UART_SCR register can be used to generate interrupt when FIFO is empty 

Query: Is this an interrupt or a mask for enabling/disabling interrupt? Do you mean to say that we should set TX_EMPTY_CTRL_IT bit in UART_SCR after handling TXFIFO_empty interrupt in UART_ISR2 register ? Which interrupt will be generated and in which register UART_IIR or UART_ISR2?

 

2. I2C

Issues arises in the following scenarios

a) two AM2634 controllers communicating via I2C (almost immediately at 400Khz and around after 1 hour on 100 khz , i2c transactions happening every 1 sec)

b) AM2634 communicating with NXP based RTC PCA2131 (random but always happen, i2c transactions every 1 sec )

c) AM2634 with LED (happens after a long time of continuous running )

Environment is interrupt heavy. Other interrupts enabled in system are for FSI, multiple UARTs , CANS, RTIs etc. I2C for inter AM2634 and RTC is assigned very high priority 1 and 2 respectively with only clock tics and a particular RTI having higher priority.

  • 0
    TI__Mastermind 26792 points

    Hi,

    UART:

    I shall get back on this by end of tomorrow.

    I2C:

    I see the issue was reported previously here:  RE: AM2634: Query on AM2634 , Can you please respond to the queries asked by the hardware team about your application and implementation?

    TEMC said:
    two AM2634 controllers communicating via I2C (almost immediately at 400Khz and around after 1 hour on 100 khz , i2c transactions happening every 1 sec)

    Is this with TI control card or launchpads? If yes, can you please provide your sample application and the SDK version it is based on.

    TEMC said:
    AM2634 with LED (happens after a long time of continuous running )

    Is this with On-board LEDs on TI eval boards?

    Regards,
    Shaunak

  • 0
    TI__Mastermind 26792 points
    TEMC said:

    Original query: Whether the line status regsister (UART_LSR) 6th bit corresponding to shift register can be mapped to any interrupt ? 

    TI reply: TX_EMPTY_CTRL_IT bit in UART_SCR register can be used to generate interrupt when FIFO is empty 

    Query: Is this an interrupt or a mask for enabling/disabling interrupt? Do you mean to say that we should set TX_EMPTY_CTRL_IT bit in UART_SCR after handling TXFIFO_empty interrupt in UART_ISR2 register ? Which interrupt will be generated and in which register UART_IIR or UART_ISR2?

    UART_LSR[6] can generate an interrupt but indirectly via the UART_SCR[3]. When you set UART_SCR[3] to enable interrupt, it means that "THE THR INTERRUPT IS GENERATED WHEN TX FIFO AND TX SHIFT REGISTER ARE EMPTY"."

    THR interrupt is generated when BOTH the TX FIFO AND the TX Shift Register are empty (i.e., it effectively maps to the condition — same as LSR Bit 6). The UART_IIR register shows THR interrupt as bit 1.

    Regards,
    Shaunak