AM263P4-Q1: Clarification on Mailbox Register Accessibility between R5 and HSM

Jidhin Angadithazha

Part Number: AM263P4-Q1

Hi Team,

I am working on custom SBL and which shall communicate with HSM ROM Boot to load HSMRt.

While going through the TRM and implementing a mailbox-based communication flow, I am facing some confusion regarding register accessibility and the interpretation of “per-core mailbox registers.”

My understanding as per TRM MBOX communication (Below snapshot).

The description of Step 7 and Step 8 is somewhat confusing.

Step 7: R5SS0_CORE0 reads the register R5SS1_CORE1_MBOX_READ_DONE.PROC3 to check for the acknowledgment.
Step 8: R5SS0_CORE0 writes 0x1 to R5SS1_CORE1_MBOX_READ_DONE.PROC3 to clear the interrupt.

However, it is unclear how this mechanism applies in the case of R5 ↔ HSM communication, since the R5 core does not have access to registers such as HSM_SOC_CTRL_HSM_MBOX_READ_DONE.

Please find the Diagram I created for R5 ↔ HSM communication ,

Could you please clarify:

Which register should the host (R5) monitor to detect the READ_DONE_ACK from the HSM core?
Will it be possible to check the Read Done ACK in Polling mode.

Thanks & Best Regards,

Jidhin Angadithazha

21 days ago