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AM62P: Inquiry regarding the TDA4VEN/AM62P DPHY -110 issue

Part Number: AM62P

Hi,
The following error frequently occurs after the device boots up:
[ 19.074376] cdns-mipi-dphy-rx 30110000.phy: DPHY wait for lane ready timeout
[ 19.082056] cdns-csi2rx 30101000.csi-bridge: Failed to configure external DPHY: -110
After checking the kernel driver, I found that the error is reported by cdns-dphy-rx.c, as shown below. What does this register mean, and what could be the reason for the frequent -110 return value in cdns_dphy_rx_wait_for_bit(reg + DPHY_ISO_CL_CTRL_L, DPHY_ISO_LANE_READY_BIT);?
 
static int cdns_dphy_rx_wait_lane_ready(struct cdns_dphy_rx *dphy,   unsigned int lanes)
  131 {
132     static const u32 data_lane_ctrl[] = {DPHY_ISO_DL_CTRL_L0,
  133                          DPHY_ISO_DL_CTRL_L1,
  134                          DPHY_ISO_DL_CTRL_L2,
  135                          DPHY_ISO_DL_CTRL_L3};
 136     void __iomem *reg = dphy->regs;
  137     unsigned int i;
  138     int ret;
  139 
  140     /* Clock lane */
  141     ret = cdns_dphy_rx_wait_for_bit(reg + DPHY_ISO_CL_CTRL_L,
  142                     DPHY_ISO_LANE_READY_BIT);
  143     if (ret) {
  144         return ret;
  145     }
  146 
  147     for (i = 0; i < lanes; i++) {
  148         ret = cdns_dphy_rx_wait_for_bit(reg + data_lane_ctrl[i],
  149                         DPHY_ISO_LANE_READY_BIT);
  150         if (ret)
  151             return ret;
  152     }
  153 
  154     return 0;
  155 }

 

                                                                                                                            
 
  • Hi Ying,

    I'll need to check internally what this register indicates since I don't find it inside the TRM. Meanwhile, can you please share the answers to the following points:

    1. What is the hardware configuration?
    2. Are you changing the cdns and j721e csi2rx drivers? If yes, please share the patch if possible.
    3. Can this be reproduced on the EVM?

    Regards,
    Jay

  • Hi,

    1. Our hardware setup is MAX96724 + MAX96717 + ISX031. This error occurs occasionally, but only when all 4 cameras are connected. We have observed this issue on both our custom AM62P and TDA4VEN boards, so we suspect it might be a hardware-related issue. However, we don't have solid evidence to prove it yet. Regarding the EVM, it will be difficult to reproduce this issue.

    2. We are currently using SDK 10.01. We have not modified the Cadence (cdns) or the TI CSI2RX (ti-csi2rx / j721e) drivers.

    3. As a workaround, I commented out the return ret; line in the driver. After doing this, the driver no longer reports the error, and we can still successfully capture the video stream. 

  • Hi Ying,

    I saw this thread:  TDA4VEN-Q1: TDA4-Ven Chip & ISX031 Adaptation Inquiry 

    I am assuming that it is the same issue as the thread here. Assuming device tree overlays with the same settings(link frequencies, data lane configuration etc):

    1. I don't think that there is any issue with the software configuration.
    2. Considering that you mentioned that 4 camera streams worked with a lower resolution and 3 streams with the full resolution, I don't believe an issue with the driver.
    3. The link frequency of 1.25GHz would be enough for 4 UYVY8 streams at 1920x1536 resolution.

    That said, I don't think I have a copy of your driver. So, if possible, please share that with me as well. Also, if there are any changes with the device tree overlay, please let me know about those as well.

    Coming to the registers that are failing. Can you please add debug prints such as the ones I am attaching in the patch below and let me know which register reads fail. This might help me understand what is the issue.

    Also, please let me know if you are changing the MMU configs for the device. Incorrect caching properties may cause an issue with the poll of the register. As an example, let's say the region is accidentally marked cached. This way, you might be polling the incorrect value even though the actual MMR has been updated.

    Regards,
    Jay

    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/908/0001_2D00_add_2D00_debug_2D00_prints_2D00_for_2D00_DPHY.patch