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AM2612: Regarding OSPI and SPI input clocks

MASAKI MIYASHITA
Prodigy 70 points

Part Number: AM2612
Other Parts Discussed in Thread: SYSCONFIG

OSPI
Looking at Figure 4-22 and Table 4-51 in the TRM, it appears that OSPI0_RCLK can be selected from various sources.
In SysConfig, the "Input Clock Frequency" for OSPI can be set to an arbitrary value; please explain its relationship with OSPI0_RCLK.

SPI
Looking at Figure 13-27 and Table 13-21 in the TRM, it appears that SPI#_FCLK can be selected from various sources.
In SysConfig, the "Clock Frequency" for MCSPI can be set to an arbitrary value; please explain its relationship with SPI#_FCLK.

  • 0
    TI__Mastermind 27222 points

    Hi Miyashi-San,

    Can you please help me with your SDK version? In the latest SDKs and Sysconfig, this has been fixed. You can select the OSPI_RCLK from the sources given in the TRM table only. It will not take any arbitrary values.

    Similarly for SPI, input clock for the IP can be selected from the pre-defined list of sources in clock-tree, the configuration inside the MCSPI instance configuration lets you configure the frequency for multiple channels. The clock tree selection is for the IP itself and not the SPI channels.

    Regards,
    Shaunak

  • 0 in reply to Shaunak Deshpande
    Prodigy 70 points

    Thank you for your reply.
    The versions are as follows:

    CCS:12.8.1.00005
    SDK:10.02.00.07
    SysConfig:1.23.0

  • +1 in reply to MASAKI MIYASHITA
    TI__Mastermind 27222 points

    HI Miyashita-San,

    I would recommend upgrading the SDK and syscfg version if possible. Else, you have to manually make sure the input clock frequencies are passed correctly. The allowed frequencies are shown in TRM (OPSI Table 4-51) and SPI (Table 4-22)

     (please note that HSDIV0_CLKOUT3 In mode2 should be 166MHz instead of 133MHz)

    Essentially, the OSPI accepts multiple clock sources (WUCPUCLK, EXT REFCLK, PLL_CORE_CLK etc), one of them can be chosen and dividers can be selected to generate a final OSPI Clock. Based on the clock source and the dividers selected, the OSPI CLK SRC register is programmed.

    Similarly, for SPI, you have multiple input clocks, you can chose one and select appropriate divider to provide the needed frequency to the module. The reason for providing multiple clock options is to have flexibility in terms of frequencies that can be achieved. 

    Regards,
    Shaunak

  • 0 in reply to Shaunak Deshpande
    Prodigy 70 points

    Thank you for your reply.